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2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor product overview 1-1 product overview introduction this manual describes samsung's S3C2440X 16/32-bit risc microprocessor. samsung?s s3c24440x is designed to provide hand-held devices and general applications with low-power, and high-performance micro- controller solution in small die size. to reduce total system cost, the S3C2440X includes the following components separate 16kb instruction and 16kb data cache, mmu to handle virtual memory management, lcd controller (stn & tft), nand flash boot loader, system man ager (chip select logic and sdram controller), 3-ch uart, 4-ch dma, 4-ch timers with pwm, i/o ports, rtc, 8-ch 10-bit adc and touch screen interface, camera interface, iic-bus interface, iis-bus interface, usb host, usb device, sd host & multi-media card interface, 2- ch spi and pll for clock generation. the S3C2440X has been developed using an arm920t core, 0.13um cmos standard cells and a memory complier. its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. it adopts a new bus architecture known as advanced micro controller bus architecture (amba). the S3C2440X offers outstanding features with its cpu core, a 16/32-bit arm920t risc processor designed by advanced risc machines, ltd. the arm920t implements mmu, amba bus, and harvard cache architecture with separate 16kb instruction and 16kb data caches, each with an 8-word line length. by providing a complete set of common system peripherals, the S3C2440X minimizes overall system costs and eliminates the need to configure additional components. the integrated on-chip functions that are described in this document include: ? 1.2v internal, 1.8v/2.5v/3.3v memory, 3.3v external i/o microprocessor with 16kb i-cache/16kb d- cache/mmu ? external memory controller (sdram control and chip select logic) ? lcd controller (up to 4k color stn and 256k color tft) with 1-ch lcd-dedicated dma ? 4-ch dmas with external request pins ? 3-ch uart (irda1.0, 64-byte tx fifo, and 64-byte rx fifo) / 2-ch spi ? 1-ch multi-master iic-bus/1-ch iis-bus controller ? sd host interface version 1.0 & multi-media card protocol version 2.11 compatible ? 2-port usb host /1- port usb device (ver 1.1) ? 4-ch pwm timers & 1-ch internal timer ? watch dog timer ? 130-bit general purpose i/o ports / 24-ch external interrupt source ? power control: normal, slow, idle and sleep mode ? 8-ch 10-bit adc and touch screen interface ? rtc with calendar function ? on-chip clock generator with pll
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-2 features architecture ? integrated system for hand-held devices and general embedded applications. ? 16/32-bit risc architecture and powerful instruction set with arm920t cpu core. ? enhanced arm architecture mmu to support wince, epoc 32 and linux. ? instruction cache, data cache, write buffer and physical address tag ram to reduce the effect of main memory bandwidth and latency on performance. ? arm920t cpu core supports the arm debug architecture. ? internal advanced microcontroller bus architecture (amba) (amba2.0, ahb/apb). system manager ? little/big endian support. ? address space: 128m bytes for each bank (total 1g bytes). ? supports programmable 8/16/32-bit data bus width for each bank. ? fixed bank start address from bank 0 to bank 6. ? programmable bank start address and bank size for bank 7. ? eight memory banks: ? six memory banks for rom, sram, and others. ? two memory banks for rom/sram/ synchronous dram. ? complete programmable access cycles for all memory banks. ? supports external wait signals to expend the bus cycle. ? supports self-refresh mode in sdram for power- down. ? supports various types of rom for booting (nor/nand flash, eeprom, and others). nand flash boot loader ? supports booting from nand flash memory. ? 4kb internal buffer for booting. ? supports storage memory for nand flash memory after booting. ? supports advanced nand flash cache memory ? 64-way set-associative cache with i-cache (16kb) and d-cache (16kb). ? 8words length per line with one valid bit and two dirty bits per line. ? pseudo random or round robin replacement algorithm. ? write-through or write-back cache operation to update the main memory. ? the write buffer can hold 16 words of data and four addresses. clock & power manager ? on-chip mpll and upll: upll generates the clock to operate usb host/device. mpll generates the clock to operate mcu at maximum 400mhz @ 1.2v. ? clock can be fed selectively to each function block by software. ? power mode : normal, slow, idle, and sleep mode normal mode : normal operating mode slow mode : low frequency clock without pll idle mode : the clock for only cpu is stopped. sleep mode : the core power including all peripherals is shut down. ? woken up by eint[15:0] or rtc alarm interrupt from sleep mode
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-3 features (continued) interrupt controller ? 59 interrupt sources (one watch dog timer, 5 timers, 9 uarts, 24 external interrupts, 4 dma, 2 rtc, 2 adc, 1 iic, 2spi,1sdi,2usb,1lcd, 1batteryfault,1 nand and 2 camera) ? level/edge mode on external interrupt source ? programmable polarity of edge and level ? supports fast interrupt request (fiq) for very urgent interrupt request timer with pulse width modulation (pwm) ? 4-ch 16-bit timer with pwm / 1-ch 16-bit internal timer with dma-based or interrupt-based operation ? programmable duty cycle, frequency, and polarity ? dead-zone generation ? supports external clock sources rtc (real time clock) ? full clock feature: msec, second, minute, hour, date, day, month, and year ? 32.768 khz operation ? alarm interrupt ? time tick interrupt general purpose input/output ports ? 24 external interrupt ports ? multiplexed input/output ports uart ? 3-channel uart with dma-based or interrupt- based operation ? supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive (tx/rx) ? supports external clocks for the uart operation (uartclk) ? programmable baud rate ? supports irda 1.0 ? loopback mode for testing ? each channel has internal 64-byte tx fifo and 64-byte rx fifo. dma controller ? 4-ch dma controller ? supports memory to memory, io to memory, memory to io, and io to io transfers ? burst transfer mode to enhance the transfer rate a/d converter & touch screen interface ? 8-ch multiplexed adc ? max. 500ksps and 10-bit resolution ? internal fet for direct touch screen interface lcd controller stn lcd displays feature ? supports 3 types of stn lcd panels: 4-bit dual scan, 4-bit single scan, 8-bit single scan display type ? supports monochrome mode, 4 gray levels, 16 gray levels, 256 colors and 4096 colors for stn lcd ? supports multiple screen size ? maximum screen size: 2048x1024 ? recommended screen size: max 800x600 ? maximum virtual screen size is 4 mbytes. ? maximum virtual screen size in 256 color mode: 4096x1024, 2048x2048, 1024x4096 and others tft(thin film transistor) color displays feature ? supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color tft ? supports 16 bpp non-palette true-color displays for color tft ? supports maximum 16m color tft at 24 bpp mode ? supports multiple screen size ? maximum screen size: 2048x1024 ? recommended screen size: max 800x600 ? maximum virtual screen size is 4mbytes. ? maximum virtual screen size in 64k color mode: 2048x1024, and others
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-4 features (continued) watchdog timer ? 16-bit watchdog timer ? interrupt request or system reset at time-out iic-bus interface ? 1-ch multi-master iic-bus ? serial, 8-bit oriented and bi-directional data transferscanbemadeatupto100kbit/sin standard mode or up to 400 kbit/s in fast mode. iis-bus interface ? 1-ch iis-bus for audio interface with dma-based operation ? serial, 8-/16-bit per channel data transfers ? 128 bytes (64-byte + 64-byte) fifo for tx/rx ? supports iis format and msb-justified data format usb host ? 2-port usb host ? complies with ohci rev. 1.0 ? compatible with usb specification version 1.1 usb device ? 1-port usb device ? 5 endpoints for usb device ? compatible with usb specification version 1.1 sd host interface ? compatible with sd memory card protocol version 1.0 ? compatible with sdio card protocol version 1.0 ? bytes fifo for tx/rx ? dma based or interrupt based operation ? compatible with multimedia card protocol version 2.11 spi interface ? compatible with 2-ch serial peripheral interface protocol version 2.11 ? 2x8 bits shift register for tx/rx ? dma-based or interrupt-based operation camera interface ? itu601/itu656-format input support (8-bit) ? ycrcb 4:2:2 to 4:2:0 down-sampling ? up to 1016 horizontal resolution support operating voltage range ? core: 1.2v ? memory :1.8v/ 2.5v/3.3v ? i/o : 3.3v operating frequency ? up to 400mhz package ? 289-fbga
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-5 block diagram arm920t arm9tdmi processor core (internal embedded ice) dd[31:0] writeback pa tag ram data mmu c13 dva[31:0] dv 2 a[31:0] instruction cache (16kb) instruction mmu external coproc interface c13 id[31:0] ipa[31:0] iv 2 a[31:0] cp15 write buffer amba bus i/f jtag data cache (16kb) wbpa[31:0] dpa[31:0] bridge & dma (4ch) clock generator (mpll) a h b b u s memory cont. sram/nor/sdram bus cont. arbitor/decode power management interrupt cont. usb host cont. extmaster lcd dma lcd cont. a p b b u s i2c gpio i2s rtc spi adc sdi/mmc usb device watchdog timer bus cont. arbitor/decode timer/pwm 0 ~ 3, 4(internal) spi0,1 uart 0, 1, 2 nand ctrl. nand flash boot loader camera interface figure 1-1. S3C2440X block diagram
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-6 pin assignments bottom view u t r p n m l k j h g f e d c b a 1234567891011121314151617 figure 1-2. S3C2440X pin assignments (289-fbga)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-7 table 1-1. 289-pin fbga pin assignments ? pin number order (sheet 1 of 3) pin number pin name pin number pin name pin number pin name a1 vddi c1 vddmop e1 nfre/gpa20 a2 scke c2 ngcs5/gpa16 e2 vssmop a3 vssi c3 ngcs2/gpa13 e3 ngcs7 a4 vssi c4 ngcs3/gpa14 e4 nwait a5 vssmop c5 noe e5 nbe3 a6 vddi c6 nsras e6 nwe a7 vssmop c7 addr4 e7 addr1 a8 addr10 c8 addr11 e8 addr6 a9 vddmop c9 addr15 e9 addr14 a10 vddi c10 addr21/gpa6 e10 addr23/gpa8 a11 vssmop c11 addr24/gpa9 e11 data2 a12 vssi c12 data1 e12 data20 a13 data3 c13 data6 e13 data19 a14 data7 c14 data11 e14 data18 a15 vssmop c15 data13 e15 data17 a16 vddi c16 data16 e16 data21 a17 data10 c17 vssi e17 data24 b1 vssmop d1 ale/gpa18 f1 vddi b2 ngcs1/gpa12 d2 ngcs6 f2 vssi b3 sclk1 d3 ngcs4/gpa15 f3 nfwe/gpa19 b4 sclk0 d4 nbe0 f4 nfce/gpa22 b5 nbe1 d5 nbe2 f5 cle/gpa17 b6 vddmop d6 nscas f6 ngcs0 b7 addr2 d7 addr7 f7 addr0/gpa0 b8 addr9 d8 addr5 f8 addr3 b9 addr12 d9 addr16/gpa1 f9 addr18/gpa3 b10 vssi d10 addr20/gpa5 f10 data4 b11 vddi d11 addr26/gpa11 f11 data5 b12 vddmop d12 data0 f12 data27 b13 vssmop d13 data8 f13 data31 b14 vddmop d14 data14 f14 data26 b15 data9 d15 data12 f15 data22 b16 vddmop d16 vssmop f16 vddi b17 data15 d17 vssmop f17 vddmop
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-8 table 1-1. 289-pin fbga pin assignments ? pin number order (sheet 2 of 3) pin number pin name pin number pin name pin number pin name g1 vssop j1 vddop l1 lend/gpc0 g2 camhref/gpj10 j2 vddiarm l2 vddiarm g3 camdata1/gpj1 j3 camclkout/gpj11 l3 nxdack0/gpb9 g4 vddalive j4 camreset/gpj12 l4 vclk/gpc1 g5 campclk/gpj8 j5 tout1/gpb1 l5 nxbreq/gpb6 g6 frnb j6 tout0/gpb0 l6 vd1/gpc9 g7 camvsync/gpj9 j7 tout2/gpb2 l7 vframe/gpc3 g8 addr8 j8 camdata6/gpj6 l8 i2ssdi/nss0/gpe3 g9 addr17/gpa2 j9 sddat3/gpe10 l9 spiclk0/gpe13 g10 addr25/gpa10 j10 eint10/nss0/gpg2 l10 eint15/spiclk1/gpg7 g11 data28 j11 txd2/nrts1/gph6 l11 eint22/gpg14 g12 data25 j12 pwren l12 xtortc g13 data23 j13 tck l13 eint2/gpf2 g14 xtipll j14 tms l14 eint5/gpf5 g15 xtopll j15 rxd2/ncts1/gph7 l15 eint6/gpf6 g16 data29 j16 tdo l16 eint7/gpf7 g17 vssi j17 vddalive l17 nrts0/gph1 h1 vssiarm k1 vssiarm m1 vline/gpc2 h2 camdata7/gpj7 k2 nxback/gpb5 m2 lcd_lpcrev/gpc6 h3 camdata4/gpj4 k3 tout3/gpb3 m3 lcd_lpcoe/gpc5 h4 camdata3/gpj3 k4 tclk0/gpb4 m4 vm/gpc4 h5 camdata2/gpj2 k5 nxdreq1/gpb8 m5 vd9/gpd1 h6 camdata0/gpj0 k6 nxdreq0/gpb10 m6 vd6/gpc14 h7 camdata5/gpj5 k7 nxdack1/gpb7 m7 vd16/spimiso1/gpd8 h8 addr13 k8 sdcmd/gpe6 m8 sddat1/gpe8 h9 addr19/gpa4 k9 spimiso0/gpe11 m9 iicsda/gpe15 h10 addr22/gpa7 k10 eint13/spimiso1/gpg5 m10 eint20/gpg12 h11 vssop1 k11 ncts0/gph0 m11 eint17/nrts1/gpg9 h12 extclk k12 vddop m12 vssa_upll h13 data30 k13 txd0/gph2 m13 vdda_upll h14 nbatt_flt k14 rxd0/gph3 m14 xtirtc h15 ntrst k15 uartclk/gph8 m15 eint3/gpf3 h16 nreset k16 txd1/gph4 m16 eint1/gpf1 h17 tdi k17 rxd1/gph5 m17 eint4/gpf4
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-9 table 1-1. 289-pin fbga pin assignments ? pin number order (sheet 3 of 3) pin number pin name pin number pin name pin number pin name n1 vssop r1 vd3/gpc11 u1 vddiarm n2 vd0/gpc8 r2 vd8/gpd0 u2 vddiarm n3 vd4/gpc12 r3 vd11/gpd3 u3 vssop n4 vd2/gpc10 r4 vd13/gpd5 u4 vssiarm n5 vd10/gpd2 r5 vd18/spiclk1/gpd10 u5 vd23/nss0/gpd15 n6 vd15/gpd7 r6 vd21 /gpd13 u6 i2ssdo/i2ssdi/gpe4 n7 vd22/nss1/gpd14 r7 i2ssclk/gpe1 u7 vssiarm n8 sdclk/gpe5 r8 sddat0/gpe7 u8 iicscl/gpe14 n9 eint8/gpg0 r9 clkout0/gph9 u9 vssop n10 eint18/ncts1/gpg10 r10 eint11/nss1/gpg3 u10 vssiarm n11 dp0 r11 eint14/spimosi1/gpg6 u11 vddiarm n12 dn1/pdn0 r12 ncon u12 eint19/tclk1/gpg11 n13 nrstout/gpa21 r13 om1 u13 eint23/gpg15 n14 mpllcap r14 ain0 u14 dp1/pdp0 n15 vdd_rtc r15 ain2 u15 vssop n16 vdda_mpll r16 ain6 u16 vref n17 eint0/gpf0 r17 vssa_mpll u17 ain1 p1 lcd_lpcrevb/gpc7 t1 vssiarm p2 vd5/gpc13 t2 vssiarm p3 vd7/gpc15 t3 vddop p4 vd12/gpd4 t4 vd17/spimosi1/gpd9 p5 vd14/gpd6 t5 vd19/gpd11 p6 vd20/gpd12 t6 vddiarm p7 i2slrck/gpe0 t7 cdclk/gpe2 p8 sddat2/gpe9 t8 vddiarm p9 spimosi0/gpe12 t9 eint9/gpg1 p10 clkout1/gph10 t10 eint16/gpg8 p11 eint12/lcd_pwren t11 eint21/gpg13 p12 dn0 t12 vddop p13 om2 t13 om3 p14 vdda_adc t14 vssa_adc p15 ain3 t15 om0 p16 ain7 t16 ain4 p17 upllcap t17 ain5
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-10 table 1-2. S3C2440X 289-pin fbga pin assignments (sheet 1 of 9) pin number pin name default function i/o state @bus req i/o state @sleep i/o state @nreset i/o type f7 addr0/gpa0 addr0 hi-z/? o(l)/? o(l) t10s e7 addr1 addr1 hi-z o(l) o(l) t10s b7 addr2 addr2 hi-z o(l) o(l) t10s f8 addr3 addr3 hi-z o(l) o(l) t10s c7 addr4 addr4 hi-z o(l) o(l) t10s d8 addr5 addr5 hi-z o(l) o(l) t10s e8 addr6 addr6 hi-z o(l) o(l) t10s d7 addr7 addr7 hi-z o(l) o(l) t10s g8 addr8 addr8 hi-z o(l) o(l) t10s b8 addr9 addr9 hi-z o(l) o(l) t10s a8 addr10 addr10 hi-z o(l) o(l) t10s c8 addr11 addr11 hi-z o(l) o(l) t10s b9 addr12 addr12 hi-z o(l) o(l) t10s h8 addr13 addr13 hi-z o(l) o(l) t10s e9 addr14 addr14 hi-z o(l) o(l) t10s c9 addr15 addr15 hi-z o(l) o(l) t10s d9 addr16/gpa1 addr16 hi-z/? o(l)/? o(l) t10s g9 addr17/gpa2 addr17 hi-z/? o(l)/? o(l) t10s f9 addr18/gpa3 addr18 hi-z/? o(l)/? o(l) t10s h9 addr19/gpa4 addr19 hi-z/? o(l)/? o(l) t10s d10 addr20/gpa5 addr20 hi-z/? o(l)/? o(l) t10s c10 addr21/gpa6 addr21 hi-z/? o(l)/? o(l) t10s h10 addr22/gpa7 addr22 hi-z/? o(l)/? o(l) t10s e10 addr23/gpa8 addr23 hi-z/? o(l)/? o(l) t10s c11 addr24/gpa9 addr24 hi-z/? o(l)/? o(l) t10s g10 addr25/gpa10 addr25 hi-z/? o(l)/? o(l) t10s d11 addr26/gpa11 addr26 hi-z/? o(l)/? o(l) t10s r14 ain0 ain0 ? ? ai r10 u17 ain1 ain1 ? ? ai r10 r15 ain2 ain2 ? ? ai r10 p15 ain3 ain3 ? ? ai r10 t16 ym/ain4 ain4 ?/? ?/? ai r10 t17 yp/ain5 yp ?/? ?/? ai r10 r16 xm/ain6 ain6 ?/? ?/? ai r10
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-11 table 1-2. S3C2440X 289-pin fbga pin assignments (sheet 2 of 9) pin number pin name default function i/o state @bus req i/o state @sleep i/o state @nreset i/o type p16 xp/ain7 xp ?/? ?/? ai r10 h6 camdata0/gpj0 gpj0 ?/? hi-z/? i t8 g3 camdata1/gpj1 gpj1 ?/? hi-z/? i t8 h5 camdata2/gpj2 gpj2 ?/? hi-z/? i t8 h4 camdata3/gpj3 gpj3 ?/? hi-z/? i t8 h3 camdata4/gpj4 gpj4 ?/? hi-z/? i t8 h7 camdata5/gpj5 gpj5 ?/? hi-z/? i t8 j8 camdata6/gpj6 gpj6 ?/? hi-z/? i t8 h2 camdata7/gpj7 gpj7 ?/? hi-z/? i t8 g5 campclk/gpj8 gpj8 ?/? hi-z/? i t8 g7 camvsync/gpj9 gpj9 ?/? hi-z/? i t8 g2 camhref/gpj10 gpj10 ?/? hi-z/? i t8 j3 campclkout/gpj11 gpj11 ?/? o(l)/? i t8 j4 camreset/gpj12 gpj12 ?/? o(l)/? i t8 d12 data0 data0 hi-z hi-z,o(l) i b12s c12 data1 data1 hi-z hi-z,o(l) i b12s e11 data2 data2 hi-z hi-z,o(l) i b12s a13 data3 data3 hi-z hi-z,o(l) i b12s f10 data4 data4 hi-z hi-z,o(l) i b12s f11 data5 data5 hi-z hi-z,o(l) i b12s c13 data6 data6 hi-z hi-z,o(l) i b12s a14 data7 data7 hi-z hi-z,o(l) i b12s d13 data8 data8 hi-z hi-z,o(l) i b12s b15 data9 data9 hi-z hi-z,o(l) i b12s a17 data10 data10 hi-z hi-z,o(l) i b12s c14 data11 data11 hi-z hi-z,o(l) i b12s d15 data12 data12 hi-z hi-z,o(l) i b12s c15 data13 data13 hi-z hi-z,o(l) i b12s d14 data14 data14 hi-z hi-z,o(l) i b12s b17 data15 data15 hi-z hi-z,o(l) i b12s c16 data16 data16 hi-z hi-z,o(l) i b12s e15 data17 data17 hi-z hi-z,o(l) i b12s e14 data18 data18 hi-z hi-z,o(l) i b12s
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-12 table 1-2. S3C2440X 289-pin fbga pin assignments (sheet 3 of 9) pin number pin name default function i/o state @bus req i/o state @sleep i/o state @nreset i/o type e13 data19 data19 hi-z hi-z,o(l) i b12s e12 data20 data20 hi-z hi-z,o(l) i b12s e16 data21 data21 hi-z hi-z,o(l) i b12s f15 data22 data22 hi-z hi-z,o(l) i b12s g13 data23 data23 hi-z hi-z,o(l) i b12s e17 data24 data24 hi-z hi-z,o(l) i b12s g12 data25 data25 hi-z hi-z,o(l) i b12s f14 data26 data26 hi-z hi-z,o(l) i b12s f12 data27 data27 hi-z hi-z,o(l) i b12s g11 data28 data28 hi-z hi-z,o(l) i b12s g16 data29 data29 hi-z hi-z,o(l) i b12s h13 data30 data30 hi-z hi-z,o(l) i b12s f13 data31 data31 hi-z hi-z,o(l) i b12s p12 dn0 dn0 ai us n11 dp0 dp0 ai us n12 dn1/pdn0 dn1 ?/? ai us u14 dp1/pdp0 dp1 ?/? ai us n17 eint0/gpf0 gpf0 ?/? hi-z/? i t8 m16 eint1/gpf1 gpf1 ?/? hi-z/? i t8 l13 eint2/gpf2 gpf2 ?/? hi-z/? i t8 m15 eint3/gpf3 gpf3 ?/? hi-z/? i t8 m17 eint4/gpf4 gpf4 ?/? hi-z/? i t8 l14 eint5/gpf5 gpf5 ?/? hi-z/? i t8 l15 eint6/gpf6 gpf6 ?/? hi-z/? i t8 l16 eint7/gpf7 gpf7 ?/? hi-z/? i t8 n9 eint8/gpg0 gpg0 ?/? hi-z/? i t8 t9 eint9/gpg1 gpg1 ?/? hi-z/? i t8 j10 eint10/nss0/gpg2 gpg2 ?/?/? hi-z/hi-z/? i t8 r10 eint11/nss1/gpg3 gpg3 ?/?/? hi-z/hi-z/? i t8 p11 eint12/lcd_pwren/gpg4 gpg4 ?/?/? hi-z/o(l)/? i t8 k10 eint13/spimiso1/gpg5 gpg5 ?/?/? hi-z/hi-z/? i tt8 r11 eint14/spimosi1/gpg6 gpg6 ?/?/? hi-z/hi-z/? i tt8 l10 eint15/spiclk1/gpg7 gpg7 ?/?/? hi-z/hi-z/? i tt8
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-13 table 1-2. S3C2440X 289-pin fbga pin assignments (sheet 4 of 9) pin number pin name default function i/o state @bus req i/o state @sleep i/o state @nreset i/o type t10 eint16/gpg8 gpg8 ?/? hi-z/? i t8 m11 eint17/nrts1/gpg9 gpg9 ?/?/? hi-z/o(h)/? i t8 n10 eint18/ncts1/gpg10 gpg10 ?/?/? hi-z/hi-z/? i t8 u12 eint19/tclk1/gpg11 gpg11 ?/?/? hi-z/hi-z/? i t12 m10 eint20/gpg12 gpg12 ?/? hi-z/? i t12 t11 eint21/gpg13 gpg13 ?/? hi-z/? i t12 l11 eint22/gpg14 gpg14 ?/? hi-z/? i t12 u13 eint23/gpg15 gpg15 ?/? hi-z/? i t12 h12 extclk extclk ? ? ai is p17 upllcap upllcap ? ? ai r50 n14 mpllcap mpllcap ? ? ai r50 h14 nbatt_flt nbatt_flt ? ? i is d4 nbe0 nbe0 hi-z hi-z,o(h) o(h) t10s b5 nbe1 nbe1 hi-z hi-z,o(h) o(h) t10s d5 nbe2 nbe2 hi-z hi-z,o(h) o(h) t10s e5 nbe3 nbe3 hi-z hi-z,o(h) o(h) t10s r12 ncon ncon ? ? i is g6 frnb frnb ? hi-z,o(l) i d2s f3 nfwe/gpa19 gpa19 o(h)/? hi-z,o(h)/? o(h) t10s e1 nfre/gpa20 gpa20 o(h)/? hi-z,o(h)/? o(h) t10s f4 nfce/gpa22 gpa21 o(h)/? hi-z,o(h)/? o(h) t10s f5 cle/gpa17 gpa17 o(l)/? hi-z,o(l)/? o(l) t10s d1 ale/gpa18 gpa18 o(l)/? hi-z,o(l)/? o(l) t10s n13 nrstout/gpa21 gpa21 ?/? o(l)/? o(l) b8 c5 noe noe hi-z hi-z,o(h) o(h) t10s h16 nreset nreset ? ? i is f6 ngcs0 ngcs0 hi-z hi-z,o(h) o(h) t10s b2 ngcs1/gpa12 gpa12 hi-z/? hi-z,o(h)/? o(h) t10s c3 ngcs2/gpa13 gpa13 hi-z/? hi-z,o(h)/? o(h) t10s c4 ngcs3/gpa14 gpa14 hi-z/? hi-z,o(h)/? o(h) t10s d3 ngcs4/gpa15 gpa15 hi-z/? hi-z,o(h)/? o(h) t10s c2 ngcs5/gpa16 gpa16 hi-z/? hi-z,o(h)/? o(h) t10s d2 ngcs6 ngcs6 hi-z hi-z,o(h) o(h) t10s
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-14 table 1-2. S3C2440X 289-pin fbga pin assignments (sheet 5 of 9) pin number pin name default function i/o state @bus req i/o state @sleep i/o state @nreset i/o type e3 ngcs7 ngcs7 hi-z hi-z,o(h) o(h) t10s d6 nscas nscas hi-z hi-z,o(h) o(h) t10s c6 nsras nsras hi-z hi-z,o(h) o(h) t10s h15 ntrst ntrst i ? i is e4 nwait nwait ? hi-z,o(l) i d2s e6 nwe nwe hi-z hi-z,o(h) o(h) t10s j6 tout0/gpb0 gpb0 ?/? o(l)/? i t8 j5 tout1/gpb1 gpb1 ?/? o(l)/? i t8 j7 tout2/gpb2 gpb2 ?/? o(l)/? i t8 k3 tout3/gpb3 gpb3 ?/? o(l)/? i t8 k4 tclk0/gpb4 gpb4 ?/? ?/? i t8 k2 nxback/gpb5 gpb5 ?/? o(h)/? i t8 l5 nxbreq/gpb6 gpb6 ?/? ?/? i t8 k7 nxdack1/gpb7 gpb7 ?/? o(h)/? i t8 k5 nxdreq1/gpb8 gpb8 ?/? ?/? i t8 l3 nxdack0/gpb9 gpb9 ?/? o(h)/? i t8 k6 nxdreq0/gpb10 gpb10 ?/? ?/? i t8 t15 om0 om0 ? ? i is r13 om1 om1 ? ? i is p13 om2 om2 ? ? i is t13 om3 om3 ? ? i is j12 pwren pwreno(h)o(l)o(h)b8 k11 ncts0/gph0 gph0 ?/? ?/? i t8 l17 nrts0/gph1 gph1 ?/? o(h)/? i t8 k13 txd0/gph2 gph2 ?/? o(h)/? i t8 k14 rxd0/gph3 gph3 ?/? ?/? i t8 k16 txd1/gph4 gph4 ?/? o(h)/? i t8 k17 rxd1/gph5 gph5 ?/? ?/? i t8 j11 txd2/nrts1/gph6 gph6 ?/?/? o(h)/o(h)/? i t8 j15 rxd2/ncts1/gph7 gph7 ?/?/? hi-z/hi-z/? i t8 k15 uartclk/gph8 gph8 ?/? hi-z/? i t8 r9 clkout0/gph9 gph9 ?/? o(l)/? i t12 p10 clkout1/gph10 gph10 ?/? o(l)/? i t12
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-15 table 1-2. S3C2440X 289-pin fbga pin assignments (sheet 6 of 9) pin number pin name default function i/o state @bus req i/o state @sleep i/o state @nreset i/o type a2 scke scke hi-z o(l) o(h) t10s b4 sclk0 sclk0 hi-z o(l) o(sclk) t12s b3 sclk1 sclk1 hi-z o(l) o(sclk) t12s p7 i2slrck/gpe0 gpe0 ?/? hi-z/? i t8 r7 i2ssclk/gpe1 gpe1 ?/? hi-z/? i t8 t7 cdclk/gpe2 gpe2 ?/? hi-z/? i t8 l8 i2ssdi/nss0/gpe3 gpe3 ?/?/? hi-z/hi-z/? i t8 u6 i2ssdo/i2ssdi/gpe4 gpe4 ?/?/? o(l)/hi-z/? i t8 n8 sdclk/gpe5 gpe5 ?/? o(l)/? i t8 k8 sdcmd/gpe6 gpe6 ?/? hi-z/? i t8 r8 sddat0/gpe7 gpe7 ?/? hi-z/? i t8 m8 sddat1/gpe8 gpe8 ?/? hi-z/? i t8 p8 sddat2/gpe9 gpe9 ?/? hi-z/? i t8 j9 sddat3/gpe10 gpe10 ?/? hi-z/? i t8 k9 spimiso0/gpe11 gpe11 ?/? hi-z/? i tt8 p9 spimosi0/gpe12 gpe12 ?/? hi-z/? i tt8 l9 spiclk0/gpe13 gpe13 ?/? hi-z/? i tt8 u8 iicscl/gpe14 gpe14 ?/? hi-z/? i d8 m9 iicsda/gpe15 gpe15 ?/? hi-z/? i d8 j13 tck tck i ? i is h17 tdi tdi i ? i is j16 tdo tdo o o o ot j14 tms tms i ? i is l1 lend/gpc0 gpc0 ?/? o(l)/? i t8 l4 vclk/gpc1 gpc1 ?/? o(l)/? i t8 m1 vline/gpc2 gpc2 ?/? o(l)/? i t8 l7 vframe/gpc3 gpc3 ?/? o(l)/? i t8 m4 vm/gpc4 gpc4 ?/? o(l)/? i t8 m3 lcd_lpcoe/gpc5 gpc5 ?/? o(l)/? i t8 m2 lcd_lpcrev/gpc6 gpc6 ?/? o(l)/? i t8 p1 lcd_lpcrevb/gpc7 gpc7 ?/? o(l)/? i t8 n2 vd0/gpc8 gpc8 ?/? o(l)/? i t8 l6 vd1/gpc9 gpc9 ?/? o(l)/? i t8
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-16 table 1-2. S3C2440X 289-pin fbga pin assignments (sheet 7 of 9) pin number pin name default function i/o state @bus req i/o state @sleep i/o state @nreset i/o type n4 vd2/gpc10 gpc10 ?/? o(l)/? i t8 r1 vd3/gpc11 gpc11 ?/? o(l)/? i t8 n3 vd4/gpc12 gpc12 ?/? o(l)/? i t8 p2 vd5/gpc13 gpc13 ?/? o(l)/? i t8 m6 vd6/gpc14 gpc14 ?/? o(l)/? i t8 p3 vd7/gpc15 gpc15 ?/? o(l)/? i t8 r2 vd8/gpd0 gpd0 ?/? o(l)/? i t8 m5 vd9/gpd1 gpd1 ?/? o(l)/? i t8 n5 vd10/gpd2 gpd2 ?/? o(l)/? i t8 r3 vd11/gpd3 gpd3 ?/? o(l)/? i t8 p4 vd12/gpd4 gpd4 ?/? o(l)/? i t8 r4 vd13/usbtxdn1/gpd5 gpd5 ?/?/? o(l)/o/? i t8 p5 vd14/usbtxdp1/gpd6 gpd6 ?/?/? o(l)/o/? i t8 n6 vd15/usboen1/gpd7 gpd7 ?/?/? o(l)/o/? i t8 m7 vd16/spimiso1/gpd8 gpd8 ?/?/? o(l)/hi-z/? i tt8 t4 vd17/spimosi1/gpd9 gpd9 ?/?/? o(l)/hi-z/? i tt8 r5 vd18/spiclk1/gpd10 gpd10 ?/?/? o(l)/hi-z/? i tt8 t5 vd19/usbrxdp1/gpd11 gpd11 ?/?/? o(l)/hi-z/? i t8 p6 vd20/usbrxdn1/gpd12 gpd12 ?/?/? o(l)/hi-z/? i t8 r6 vd21/usbrxd1/gpd13 gpd13 ?/?/? o(l)/hi-z/? i t8 n7 vd22/nss1/gpd14 gpd14 ?/?/? o(l)/hi-z/? i t8 u5 vd23/nss0/gpd15 gpd15 ?/?/? o(l)/hi-z/? i t8 u16 vref vref ? ? ai ia g14 xtipll xtipll ? ? ai m26 m14 xtirtc xtirtc ? ? ai nc g15 xtopll xtopll ? ? ao m26 l12 xtortc xtortc ? ? ao nc n15 vdd_rtc vdd_rtc p p p drtc p14 vdda_adc vdda_adc p p p d33t n16 vdda_mpll vdda_mpll p p p d33t m13 vdda_upll vdda_upll p p p d33t g4 vddalive vddalive p p p d12i j17 vddalive vddalive p p p d12i
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-17 table 1-2. S3C2440X 289-pin fbga pin assignments (sheet 8 of 9) pin number pin name default function i/o state @bus req i/o state @sleep i/o state @nreset i/o type a1 vddi vddi p p p d12c a10 vddi vddi p p p d12c a16 vddi vddi p p p d12c a6 vddi vddi p p p d12c b11 vddi vddi p p p d12c f1 vddi vddi p p p d12c f16 vddi vddi p p p d12c j2 vddiarm vddiarm p p p d12c l2 vddiarm vddiarm p p p d12c t6 vddiarm vddiarm p p p d12c t8 vddiarm vddiarm p p p d12c u1 vddiarm vddiarm p p p d12c u11 vddiarm vddiarm p p p d12c u2 vddiarm vddiarm p p p d12c a9 vddmop vddmop p p p d33o b12 vddmop vddmop p p p d33o b14 vddmop vddmop p p p d33o b16 vddmop vddmop p p p d33o b6 vddmop vddmop p p p d33o c1 vddmop vddmop p p p d33o f17 vddmop vddmop p p p d33o j1 vddop vddop p p p d33o t12 vddop vddop p p p d33o t3 vddop vddop p p p d33o k12 vddop vddop p p p d33o t14 vssa_adc vssa_adc p p p st r17 vssa_mpll vssa_mpll p p p st m12 vssa_upll vssa_upll p p p st a12 vssi vssi p p p si a3 vssi vssi p p p si a4 vssi vssi p p p si b10 vssi vssi p p p si c17 vssi vssi p p p si
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-18 table 1-2. S3C2440X 289-pin fbga pin assignments (sheet 9 of 9) pin number pin name default function i/o state @bus req i/o state @sleep i/o state @nreset i/o type f2 vssi vssi p p p si g17 vssi vssi p p p si h1 vssiarm vssiarm p p p si k1 vssiarm vssiarm p p p si t1 vssiarm vssiarm p p p si t2 vssiarm vssiarm p p p si u10 vssiarm vssiarm p p p si u4 vssiarm vssiarm p p p si u7 vssiarm vssiarm p p p si a11 vssmop vssmop p p p so a15 vssmop vssmop p p p so a5 vssmop vssmop p p p so a7 vssmop vssmop p p p so b1 vssmop vssmop p p p so b13 vssmop vssmop p p p so d16 vssmop vssmop p p p so d17 vssmop vssmop p p p so e2 vssmop vssmop p p p so g1 vssop vssop p p p so n1 vssop vssop p p p so u15 vssop vssop p p p so u3 vssop vssop p p p so u9 vssop vssop p p p so h11 vssop vssop p p p so
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-19 note: 1. the @bus req. shows the pin state at the external bus, which is used by the other bus master. 2. ' ? ? mark indicates the unchanged pin state at bus request mode. 3. hi-z or pre means hi-z or early state and it is determined by the setting of misccr register. 4. ai/ao means analog input/analog output. 5. p, i, and o mean power, input and output respectively. 6. the i/o state @nreset shows the pin status in the @nreset duration below. nreset fclk @nreset 4fclk
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-20 7. the table below shows i/o types and the descriptions. i/o type descriptions d12i(vdd12ih) 1.2v vdd for alive power d12c(vdd12ih_core), si(vssih) 1.2v vdd/vss for internal logic d33o(vdd33oph), so(vssoph) 3.3v vdd/vss for external logic d33t(vdd33th_abb), st(vssbbh_abb) 3.3v vdd/vss for analog circuitry drtc(vdd30th_rtc) 3.0v vdd for rtc power t8(phbsu100ct8sm) bi-directional pad, lvcmos schmitt-trigger, 100kohm pull-up resistor with control, tri-state, io=8ma is(phis) input pad, lvcmos schmitt-trigger level us(pbusb0) usb pad t10(phtot10cd) 5v tolerant output pad, tri-state . ot(phot8) output pad, tri-state, io=8ma b8(phob8) output pad, io=8ma t16(phot16sm) output pad, tri-state, medium slew rate, io=16ma r10(phiar10_abb) analog input pad with 10-ohm resistor ia(phia_abb) analog input pad gp(phgpad_option) pad for analog pin m26(phsoscm26_2440) oscillator cell with enable and feedback resistor tt8(phtbsu100ct8sm) 5v tolerant bi-directional pad, lvcmos schmitt-trigger, 100kohm pull-up resistor with control, tri -state, medium slew rate, io=8ma t12(phbsu100ct12sm) bi-directional pad, lvcmos schmitt-trigger, 100kohm pull-up resistor with control, tri-state, io=12ma d2(phtod2) 5v tolerant output pad , open drain , io=2ma d8(phbsd8sm) bi-directional pad, lvcmos schmitt-trigger, open drain, io=8ma t10s(phtot10cd_10_2440x) 5v tolerant output pad, lvcmos , tri -state, output drive strenth control, io=4,6,8,10ma b12s(phtbsu100ct12cd_12_2440x) 5v tolerant bi-directional pad, lvcmos schmitt-trigger, 100kohm pull-up resistor with control, tri -state,output drive strenth control, io=6,8,10,12ma d2s(phtbsd2_2440x) 5v tolerant bi-directional pad, lvcmos schmitt-trigger, open-drain, output drive strenth ignore, r50(phoar50_abb) analog output pad, 50kohm resistor, separated bulk-bias t12s(phtot12cd_12_2440x) 5v tolerant output pad, lvcmos , tri -state, output drive strenth control, io=6,8,12,16ma nc(phnc) no connection pad
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-21 signal descriptions table 1-3. S3C2440X signal descriptions (sheet 1 of 6) signal i/o descriptions bus controller om[1:0] i om[1:0] sets S3C2440X in the test mode, which is used only at fabrication. also, it determines the bus width of ngcs0. the pull-up/down resistor determines the logic level during reset cycle. 00:nand-boot 01:16-bit 10:32-bit 11:test mode addr[26:0] o addr[26:0] (address bus) outputs the memory address of the corresponding bank . data[31:0] io data[31:0] (data bus) inputs data during memory read and outputs data during memory write. the bus width is programmable among 8/16/32-bit. ngcs[7:0] o ngcs[7:0] (general chip select) are activated when the address of a memory is within the address region of each bank. the number of access cycles and the bank size can be programmed. nwe o nwe (write enable) indicates that the current bus cycle is a write cycle. noe o noe (output enable) indicates that the current bus cycle is a read cycle. nxbreq i nxbreq (bus hold request) allows another bus master to request control of the local bus. back active indicates that bus control has been granted. nxback o nxback (bus hold acknowledge) indicates that the S3C2440X has surrendered control of the local bus to another bus master. nwait i nwait requests to prolong a current bus cycle. as long as nwait is l, the current bus cycle cannot be completed. sdram/sram nsras o sdram row address strobe nscas o sdram column address strobe nscs[1:0] o sdram chip select dqm[3:0] o sdram data mask sclk[1:0] o sdram clock scke o sdram clock enable nbe[3:0] o upper byte/lower byte enable(in case of 16-bit sram) nwbe[3:0] o write byte enable nand flash cle o command latch enable ale o address latch enable nfce o nand flash chip enable nfre o nand flash read enable nfwe o nand flash write enable ncon i nand flash configuration frnb i nand flash ready/busy * if nand flash controller isn?t used, it has to be pull-up. (3.3v)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-22 table 1-3. S3C2440X signal descriptions (sheet 2 of 6) signal i/o descriptions lcd control unit vd[23:0] o stn/tft/sec tft: lcd data bus lcd_pwren o stn/tft/sec tft: lcd panel power enable control signal vclk o stn/tft: lcd clock signal vframe o stn: lcd frame signal vline o stn: lcd line signal vm o stn: vm alternates the polarity of the row and column voltage vsync o tft: vertical synchronous signal hsync o tft: horizontal synchronous signal vden o tft: data enable signal lend o tft: line end signal stv o sec tft: sec(samsung electronics company) tft lcd panel control signal cpv o sec tft: sec(samsung electronics company) tft lcd panel control signal lcd_hclk o sec tft: sec(samsung electronics company) tft lcd panel control signal tp o sec tft: sec(samsung electronics company) tft lcd panel control signal sth o sec tft: sec(samsung electronics company) tft lcd panel control signal lcd_lpcoe o sec tft: timing control signal for specific tft lcd lcd_lpcrev o sec tft: timing control signal for specific tft lcd lcd_lpcrevb o sec tft: timing control signal for specific tft lcd camera interface camreset o software reset to the camera camclkout o master clock to the camera campclk i pixel clock from camera camhref i horizontal sync signal from camera camvsync i vertical sync signal from camera camdata[7:0] i pixel data for ycbcr interrupt control unit eint[23:0] i external interrupt request dma nxdreq[1:0] i external dma request nxdack[1:0] o external dma acknowledge
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-23 table 1-3. S3C2440X signal descriptions (sheet 3 of 6) signal i/o descriptions uart rxd[2:0] i uart receives data input txd[2:0] o uart transmits data output ncts[1:0] i uart clear to send input signal nrts[1:0] o uart request to send output signal uartclk i uart clock signal adc ain[7:0] ai adc input[7:0]. if it isn?t used pin, it has to be low (ground). vref ai adc vref iic-bus iicsda io iic-bus data iicscl io iic-bus clock iis-bus i2slrck io iis-bus channel select clock i2ssdo o iis-bus serial data output i2ssdi i iis-bus serial data input i2ssclk io iis-bus serial clock cdclk o codec system clock touch screen nxpon o plus x-axis on-off control signal xmon o minus x-axis on-off control signal nypon o plus y-axis on-off control signal ymon o minus y-axis on-off control signal usb host dn[1:0] io data(?) from usb host dp[1:0] io data(+) from usb host usb device pdn0 io data(?) for usb peripheral pdp0 io data(+) for usb peripheral spi spimiso[1:0] io spimiso is the master data input line, when spi is configured as a master. when spi is configured as a slave, these pins reverse its role. spimosi[1:0] io spimosi is the master data output line, when spi is configured as a master. when spi is configured as a slave, these pins reverse its role. spiclk[1:0] io spi clock nss[1:0] i spi chip select(only for slave mode)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-24 table 1-3. S3C2440X signal descriptions (sheet 4 of 6) signal i/o description sd sddat[3:0] io sd receive/transmit data sdcmd io sd receive response/ transmit command sdclk o sd clock general port gpn[116:0] io general input/output ports (some ports are output only) timmer/pwm tout[3:0] o timer output[3:0] tclk[1:0] i external timer clock input jtag test logic ntrst i ntrst(tap controller reset) resets the tap controller at start. if debugger is used, a 10k pull-up resistor has to be connected. if debugger(black ice) is not used, ntrst pin must be issued by a low active pulse(typically connected to nreset). tms i tms (tap controller mode select) controls the sequence of the tap controller's states. a 10k pull-up resistor has to be connected to tms pin. tck i tck (tap controller clock) provides the clock input for the jtag logic. a 10k pull-up resistor must be connected to tck pin. tdi i tdi (tap controller data input) is the serial input for test instructions and data. a 10k pull-up resistor must be connected to tdi pin. tdo o tdo (tap controller data output) is the serial output for test instructions and data.
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-25 table 1-3. S3C2440X signal descriptions (sheet 5 of 6) signal i/o description reset, clock & power xtopll ao crystal output for internal osc circuit. when om[3:2] = 00b, xtipll is used for mpll clk source and upll clk source. when om[3:2] = 01b, xtipll is used for mpll clk source only. when om[3:2] = 10b, xtipll is used for upll clk source only. if it isn't used, it has to be a floating pin. mpllcap ai loop filter capacitor for main clock. upllcap ai loop filter capacitor for usb clock. xtirtc ai 32 khz crystal input for rtc. if it isn?t used, it has to be high (3.3v). xtortc ao 32 khz crystal output for rtc. if it isn?t used, it has to be float. clkout[1:0] o clock output signal. the clksel of misccr register configures the clock output mode among the mpll clk, upll clk, fclk, hclk, pclk. nreset st nreset suspends any operation in progress and places S3C2440X into a known reset state. for a reset, nreset must be held to l level for at least 4 fclk after the processor power has been stabilized. nrstout o for external device reset control(nrstout = nreset & nwdtrst & sw_reset) pwren o 1.2v core power on-off control signal nbatt_flt i probe for battery state(does not wake up at sleep mode in case of low battery state). if it isn?t used, it has to be high (3.3v). om[3:2] i om[3:2] determines how the clock is made. om[3:2] = 00b, crystal is used for mpll clk source and upll clk source. om[3:2] = 01b, crystal is used for mpll clk source and extclk is used for upll clk source. om[3:2] = 10b, extclk is used for mpll clk source and crystal is used for upll clk source. om[3:2] = 11b, extclk is used for mpll clk source and upll clk source. extclk i external clock source. when om[3:2] = 11b, extclk is used for mpll clk source and upll clk source. when om[3:2] = 10b, extclk is used for mpll clk source only. when om[3:2] = 01b, extclk is used for upll clk source only. if it isn't used, it has to be high (3.3v). xtipll ai crystal input for internal osc circuit. when om[3:2] = 00b, xtipll is used for mpll clk source and upll clk source. when om[3:2] = 01b, xtipll is used for mpll clk source only. when om[3:2] = 10b, xtipll is used for upll clk source only. if it isn't used, xtipll has to be high (3.3v).
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-26 table 1-3. S3C2440X signal descriptions (sheet 6 of 6) signal i/o description power vddalive p S3C2440X reset block and port status register vdd(1.2v). it should be always supplied whether in normal mode or in sleep mode. vddi/vddiarm p S3C2440X core logic vdd(1.2v) for cpu. vssi/vssiarm p S3C2440X core logic vss vddi_mpll p S3C2440X mpll analog and digital vdd (1.2 v). vssi_mpll p S3C2440X mpll analog and digital vss. vddop p S3C2440X i/o port vdd(3.3v) vddmop p S3C2440X memory i/o vdd 3.3v : sclk up to 100mhz 2.5v : sclk up to 80mhz vssop p S3C2440X i/o port vss rtcvdd p rtc vdd ( 3.0v ) (this pin must be connected to power properly if rtc isn't used) vddi_upll p S3C2440X upll analog and digital vdd (1.2v) vssi_upll p S3C2440X upll analog and digital vss vdda_adc p S3C2440X adc vdd(3.3v) vssa_adc p S3C2440X adc vss note: 1. i/o means input/output. 2. ai/ao means analog input/analog output. 3. st means schmitt-trigger. 4. p means power.
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-27 S3C2440X special registers table 1-4. S3C2440X special registers (sheet 1 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function memory controller bwscon 0x48000000 w r/w bus width & wait status control bankcon0 0x48000004 boot rom control bankcon1 0x48000008 bank1 control bankcon2 0x4800000c bank2 control bankcon3 0x48000010 bank3 control bankcon4 0x48000014 bank4 control bankcon5 0x48000018 bank5 control bankcon6 0x4800001c bank6 control bankcon7 0x48000020 bank7 control refresh 0x48000024 dram/sdram refresh control banksize 0x48000028 flexible bank size mrsrb6 0x4800002c mode register set for sdram bank6 mrsrb7 0x48000030 mode register set for sdram bank7
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-28 table 1-4. S3C2440X special registers (sheet 2 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function usb host controller hcrevision 0x49000000 w control and status group hccontrol 0x49000004 hccommonstatus 0x49000008 hcinterruptstatus 0x4900000c hcinterruptenable 0x49000010 hcinterruptdisable 0x49000014 hchcca 0x49000018 memory pointer group hcperiodcuttented 0x4900001c hccontrolheaded 0x49000020 hccontrolcurrented 0x49000024 hcbulkheaded 0x49000028 hcbulkcurrented 0x4900002c hcdonehead 0x49000030 hcrminterval 0x49000034 frame counter group hcfmremaining 0x49000038 hcfmnumber 0x4900003c hcperiodicstart 0x49000040 hclsthreshold 0x49000044 hcrhdescriptora 0x49000048 root hub group hcrhdescriptorb 0x4900004c hcrhstatus 0x49000050 hcrhportstatus1 0x49000054 hcrhportstatus2 0x49000058 interrupt controller srcpnd 0x4a000000 w r/w interrupt request status intmod 0x4a000004 w interrupt mode control intmsk 0x4a000008 r/w interrupt mask control priority 0x4a00000c w irq priority control intpnd 0x4a000010 r/w interrupt request status intoffset 0x4a000014 r interrupt request source offset subsrcpnd 0x4a000018 r/w sub source pending intsubmsk 0x4a00001c r/w interrupt sub mask
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-29 table 1-4. S3C2440X special registers (sheet 3 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function dma disrc0 0x4b000000 w r/w dma 0 initial source disrcc0 0x4b000004 dma 0 initial source control didst0 0x4b000008 dma 0 initial destination didstc0 0x4b00000c dma 0 initial destination control dcon0 0x4b000010 dma 0 control dstat0 0x4b000014 r dma 0 count dcsrc0 0x4b000018 dma 0 current source dcdst0 0x4b00001c dma 0 current destination dmasktrig0 0x4b000020 r/w dma 0 mask trigger disrc1 0x4b000040 dma 1 initial source disrcc1 0x4b000044 dma 1 initial source control didst1 0x4b000048 dma 1 initial destination didstc1 0x4b00004c dma 1 initial destination control dcon1 0x4b000050 dma 1 control dstat1 0x4b000054 r dma 1 count dcsrc1 0x4b000058 dma 1 current source dcdst1 0x4b00005c dma 1 current destination dmasktrig1 0x4b000060 r/w dma 1 mask trigger disrc2 0x4b000080 dma 2 initial source disrcc2 0x4b000084 dma 2 initial source control didst2 0x4b000088 dma 2 initial destination didstc2 0x4b00008c dma 2 initial destination control dcon2 0x4b000090 dma 2 control dstat2 0x4b000094 r dma 2 count dcsrc2 0x4b000098 dma 2 current source dcdst2 0x4b00009c dma 2 current destination dmasktrig2 0x4b0000a0 r/w dma 2 mask trigger disrc3 0x4b0000c0 w r/w dma 3 initial source disrcc3 0x4b0000c4 dma 3 initial source control didst3 0x4b0000c8 dma 3 initial destination didstc3 0x4b0000cc dma 3 initial destination control dcon3 0x4b0000d0 dma 3 control dstat3 0x4b0000d4 r dma 3 count dcsrc3 0x4b0000d8 dma 3 current source dcdst3 0x4b0000dc dma 3 current destination dmasktrig3 0x4b0000e0 r/w dma 3 mask trigger
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-30 table 1-4. S3C2440X special registers (sheet 4 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function clock & power management locktime 0x4c000000 w r/w pll lock time counter mpllcon 0x4c000004 mpll control upllcon 0x4c000008 upll control clkcon 0x4c00000c clock generator control clkslow 0x4c000010 slow clock control clkdivn 0x4c000014 clock divider control camdivn 0x4c000018 camera clock divider control lcd controller lcdcon1 0x4d000000 w r/w lcd control 1 lcdcon2 0x4d000004 lcd control 2 lcdcon3 0x4d000008 lcd control 3 lcdcon4 0x4d00000c lcd control 4 lcdcon5 0x4d000010 lcd control 5 lcdsaddr1 0x4d000014 stn/tft: frame buffer start address1 lcdsaddr2 0x4d000018 stn/tft: frame buffer start address2 lcdsaddr3 0x4d00001c stn/tft: virtual screen address set redlut 0x4d000020 stn: red lookup table greenlut 0x4d000024 stn: green lookup table bluelut 0x4d000028 stn: blue lookup table dithmode 0x4d00004c stn: dithering mode tpal 0x4d000050 tft: temporary palette lcdintpnd 0x4d000054 lcd interrupt pending lcdsrcpnd 0x4d000058 lcd interrupt source lcdintmsk 0x4d00005c lcd interrupt mask tconsel 0x4d000060 tcon(lpc3600/lcc3600) control
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-31 table 1-4. S3C2440X special registers (sheet 5 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function nand flash nfconf 0x4e000000 w r/w nand flash configuration nfcont 0x4e000004 nand flash control nfcmd 0x4e000008 nand flash command nfaddr 0x4e00000c nand flash address nfdata 0x4e000010 nand flash data nfmecc0 0x4e000014 nand flash main area ecc0/1 nfmecc1 0x4e000018 nand flash main area ecc2/3 nfsecc 0x4e00001c nand flash spare area ecc nfstat 0x4e000020 nand flash operation status nfestat0 0x4e000024 nand flash ecc status for i/o[7:0] nfestat1 0x4e000028 nand flash ecc status for i/o[15:8] nfmecc0 0x4e00002c r nand flash main area ecc0 status nfmecc1 0x4e000030 nand flash main area ecc1 status nfsecc 0x4e000034 nand flash spare area ecc status nfsblk 0x4e000038 r/w nand flash start block address nfeblk 0x4e00003c nand flash end block address
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-32 table 1-4. S3C2440X special registers (sheet 6 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function camera interface asize 0x4f000000 w w a-port image size stay1 0x4f000004 r/w y start address for 1 st ping-pong memory of a- port image stay2 0x4f000008 y start address for 2 nd ping-pong memory of a- port image stay3 0x4f00000c y start address for 3 rd ping-pong memory of a- port image stay4 0x4f000010 y start address for 4 th ping-pong memory of a- port image ayburst 0x4f000014 w a-port image y data burst length acbburst 0x4f000018 a-port image cb data burst length acrburst 0x4f00001c a-port image cr data burst length bsize 0x4f000020 b-port image size stby1 0x4f000024 y start address for 1 st ping-pong memory of b- port image stby2 0x4f000028 y start address for 2 nd ping-pong memory of b- port image stby3 0x4f00002c y start address for 3 rd ping-pong memory of b- port image stby4 0x4f000030 y start address for 4 th ping-pong memory of b- port image byburst 0x4f000034 b-port image y data burst length bcbburst 0x4f000038 b-port image cb data burst length bcrburst 0x4f00003c b-port image cr data burst length adistwidth 0x4f000040 a last href distance width bdistwidth 0x4f000044 b last href distance width yratio 0x4f00004c y scale ratio cratio 0x4f000050 c scale ratio yoriginal 0x4f000054 y original size coriginal 0x4f00005c c original size stacb1 0x4f000074 a cb 1 start address stacb2 0x4f000078 a cb 2 start address stacb3 0x4f00007c a cb 3 start address stacb4 0x4f000080 a cb 4 start address
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-33 table 1-4. S3C2440X special registers (sheet 7 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function camera interface(continued) stacr1 0x4f000084 w w a cr 1 start address stacr2 0x4f000088 a cr 2 start address stacr3 0x4f00008c a cr 3 start address stacr4 0x4f000090 a cr 4 start address stbcb1 0x4f00009c b cb 1 start address stbcb2 0x4f0000a0 b cb 2 start address stbcb3 0x4f0000a4 b cb 3 start address stbcb4 0x4f0000a8 b cb 4 start address stbcr1 0x4f0000ac b cr 1 start address stbcr2 0x4f0000b0 b cr 2 start address stbcr3 0x4f0000b4 b cr 3 start address stbcr4 0x4f0000b8 b cr 4 start address ctrl 0x4f0000bc control register rdstat 0x4f000000 r status read register rdstay 0x4f000014 a y start address read rdstacb 0x4f000018 a cb start address read rdstacr 0x4f00001c a cr start address read rdstacb1 0x4f000020 a cb1 start address read rdstacr1 0x4f000024 a cr1 start address read rdstby1 0x4f000028 b y1 start address read rdstby2 0x4f00002c b y2 start address read rdstby3 0x4f000030 b y3 start address read rdstby4 0x4f000034 b y4 start address read rdstby 0x4f000038 b y start address read rdstbcb 0x4f00003c b cb start address read rdstbcr 0x4f000040 b cr start address read rdstbcb1 0x4f000044 b cb1 start address read rdstbcr1 0x4f000048 b cr1 start address read rdadistwidth 0x4f00004c a last href distance width rdbdistwidth 0x4f000050 b last href distance width
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-34 table 1-4. S3C2440X special registers (sheet 8 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function uart ulcon0 0x50000000 w r/w uart0linecontrol ucon0 0x50000004 uart 0 control ufcon0 0x50000008 uart 0 fifo control umcon0 0x5000000c uart 0 modem control utrstat0 0x50000010 r uart 0 tx/rx status uerstat0 0x50000014 uart 0 rx error status ufstat0 0x50000018 uart 0 fifo status umstat0 0x5000001c uart 0 modem status utxh0 0x50000023 0x50000020 b w uart 0 transmission hold urxh0 0x50000027 0x50000024 r uart 0 receive buffer ubrdiv0 0x50000028 w r/w uart 0 baud rate divisor ulcon1 0x50004000 uart 1 line control ucon1 0x50004004 uart 1 control ufcon1 0x50004008 uart 1 fifo control umcon1 0x5000400c uart 1 modem control utrstat1 0x50004010 r uart 1 tx/rx status uerstat1 0x50004014 uart 1 rx error status ufstat1 0x50004018 uart 1 fifo status umstat1 0x5000401c uart 1 modem status utxh1 0x50004023 0x50004020 b w uart 1 transmission hold urxh1 0x50004027 0x50004024 r uart 1 receive buffer ubrdiv1 0x50004028 w r/w uart 1 baud rate divisor ulcon2 0x50008000 uart 2 line control ucon2 0x50008004 uart 2 control ufcon2 0x50008008 uart 2 fifo control utrstat2 0x50008010 r uart 2 tx/rx status uerstat2 0x50008014 uart 2 rx error status ufstat2 0x50008018 uart 2 fifo status utxh2 0x50008023 0x50008020 b w uart 2 transmission hold urxh2 0x50008027 0x50008024 r uart 2 receive buffer ubrdiv2 0x50008028 w r/w uart 2 baud rate divisor
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-35 table 1-4. S3C2440X special registers (sheet 9 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function pwm timer tcfg0 0x51000000 w r/w timer configuration tcfg1 0x51000004 timer configuration tcon 0x51000008 timer control tcntb0 0x5100000c timer count buffer 0 tcmpb0 0x51000010 timer compare buffer 0 tcnto0 0x51000014 r timer count observation 0 tcntb1 0x51000018 r/w timer count buffer 1 tcmpb1 0x5100001c timer compare buffer 1 tcnto1 0x51000020 r timer count observation 1 tcntb2 0x51000024 r/w timer count buffer 2 tcmpb2 0x51000028 timer compare buffer 2 tcnto2 0x5100002c r timer count observation 2 tcntb3 0x51000030 r/w timer count buffer 3 tcmpb3 0x51000034 timer compare buffer 3 tcnto3 0x51000038 r timer count observation 3 tcntb4 0x5100003c r/w timer count buffer 4 tcnto4 0x51000040 r timer count observation 4
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-36 table 1-4. S3C2440X special registers ( sheet 10 of 14)) register name address (b. endian) address (l. endian) acc. unit read/w rite function usb device func_addr_reg 0x52000143 0x52000140 b r/w function address pwr_reg 0x52000147 0x52000144 power management ep_int_reg 0x5200014b 0x52000148 ep interrupt pending and clear usb_int_reg 0x5200015b 0x52000158 usb interrupt pending and clear ep_int_en_reg 0x5200015f 0x5200015c interrupt enable usb_int_en_reg 0x5200016f 0x5200016c interrupt enable frame_num1_reg 0x52000173 0x52000170 r frame number lower byte frame_num2_reg 0x52000177 0x52000174 frame number higher byte index_reg 0x5200017b 0x52000178 r/w register index ep0_csr 0x52000187 0x52000184 endpoint 0 status in_csr1_reg 0x52000187 0x52000184 in endpoint control status in_csr2_reg 0x5200018b 0x52000188 in endpoint control status maxp_reg 0x52000183 0x52000180 endpoint max packet out_csr1_reg 0x52000193 0x52000190 out endpoint control status out_csr2_reg 0x52000197 0x52000194 out endpoint control status out_fifo_cnt1_reg 0x5200019b 0x52000198 r endpoint out write count out_fifo_cnt2_reg 0x5200019f 0x5200019c endpoint out write count ep0_fifo 0x520001c3 0x520001c0 r/w endpoint 0 fifo ep1_fifo 0x520001c7 0x520001c4 endpoint 1 fifo ep2_fifo 0x520001cb 0x520001c8 endpoint 2 fifo ep3_fifo 0x520001cf 0x520001cc endpoint 3 fifo ep4_fifo 0x520001d3 0x520001d0 endpoint 4 fifo ep1_dma_con 0x52000203 0x52000200 ep1 dma interface control ep1_dma_unit 0x52000207 0x52000204 ep1 dma tx unit counter ep1_dma_fifo 0x5200020b 0x52000208 ep1 dma tx fifo counter ep1_dma_ttc_l 0x5200020f 0x5200020c ep1 dma total tx counter ep1_dma_ttc_m 0x52000213 0x52000210 ep1 dma total tx counter ep1_dma_ttc_h 0x52000217 0x52000214 ep1 dma total tx counter
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-37 table 1-4. S3C2440X special registers (sheet 11 of 14) register name address (b. endian) address (l. endian) acc. unit read/w rite function usb device (continued) ep2_dma_con 0x5200021b 0x52000218 b r/w ep2 dma interface control ep2_dma_unit 0x5200021f 0x5200021c ep2 dma tx unit counter ep2_dma_fifo 0x52000223 0x52000220 ep2 dma tx fifo counter ep2_dma_ttc_l 0x52000227 0x52000224 ep2 dma total tx counter ep2_dma_ttc_m 0x5200022b 0x52000228 ep2 dma total tx counter ep2_dma_ttc_h 0x5200022f 0x5200022c ep2 dma total tx counter ep3_dma_con 0x52000243 0x52000240 ep3 dma interface control ep3_dma_unit 0x52000247 0x52000244 ep3 dma tx unit counter ep3_dma_fifo 0x5200024b 0x52000248 ep3 dma tx fifo counter ep3_dma_ttc_l 0x5200024f 0x5200024c ep3 dma total tx counter ep3_dma_ttc_m 0x52000253 0x52000250 ep3 dma total tx counter ep3_dma_ttc_h 0x52000257 0x52000254 ep3 dma total tx counter ep4_dma_con 0x5200025b 0x52000258 ep4 dma interface control ep4_dma_unit 0x5200025f 0x5200025c ep4 dma tx unit counter ep4_dma_fifo 0x52000263 0x52000260 ep4 dma tx fifo counter ep4_dma_ttc_l 0x52000267 0x52000264 ep4 dma total tx counter ep4_dma_ttc_m 0x5200026b 0x52000268 ep4 dma total tx counter ep4_dma_ttc_h 0x5200026f 0x5200026c ep4 dma total tx counter watchdog timer wtcon 0x53000000 w r/w watchdog timer mode wtdat 0x53000004 watchdog timer data wtcnt 0x53000008 watchdog timer count iic iiccon 0x54000000 w r/w iic control iicstat 0x54000004 iic status iicadd 0x54000008 iic address iicds 0x5400000c iic data shift iiclc 0x54000010 iic multi-master line control iis iiscon 0x55000000,02 0x55000000 hw,w r/w iis control iismod 0x55000004,06 0x55000004 iis mode iispsr 0x55000008,0a 0x55000008 iis prescaler iisfcon 0x5500000c,0e 0x5500000c iis fifo control iisfifo 0x55000012 0x55000010 hw iis fifo entry
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-38 table 1-4. S3C2440X special registers (sheet 12 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function i/o port gpacon 0x56000000 w r/w port a control gpadat 0x56000004 port a data gpbcon 0x56000010 port b control gpbdat 0x56000014 port b data gpbup 0x56000018 pull-up control b gpccon 0x56000020 port c control gpcdat 0x56000024 port c data gpcup 0x56000028 pull-up control c gpdcon 0x56000030 port d control gpdda1t 0x56000034 port d data gpdup 0x56000038 pull-up control d gpecon 0x56000040 port e control gpedat 0x56000044 port e data gpeup 0x56000048 pull-up control e gpfcon 0x56000050 port f control gpfdat 0x56000054 port f data gpfup 0x56000058 pull-up control f gpgcon 0x56000060 port g control gpgdat 0x56000064 port g data gpgup 0x56000068 pull-up control g gphcon 0x56000070 port h control gphdat 0x56000074 port h data gphup 0x56000078 pull-up control h gpjcon 0x560000d0 port j control gpjdat 0x560000d4 port j data gpjup 0x560000d8 pull-up control j misccr 0x56000080 miscellaneous control dclkcon 0x56000084 dclk0/1 control extint0 0x56000088 external interrupt control register 0 extint1 0x5600008c external interrupt control register 1 extint2 0x56000090 external interrupt control register 2
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X product overview 1-39 table 1-4. S3C2440X special registers (sheet 13 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function i/o port (continued) eintflt0 0x56000094 wr/wreserved eintflt1 0x56000098 reserved eintflt2 0x5600009c external interrupt filter control register 2 eintflt3 0x560000a0 external interrupt filter control register 3 eintmask 0x560000a4 external interrupt mask eintpend 0x560000a8 external interrupt pending gstatus0 0x560000ac r external pin status gstatus1 0x560000b0 r/w chip id gstatus2 0x560000b4 reset status gstatus3 0x560000b8 inform register gstatus4 0x560000bc inform register mslcon 0x560000cc memory sleep control register rtc rtccon 0x57000043 0x57000040 b r/w rtc control ticnt 0x57000047 0x57000044 tick time count rtcalm 0x57000053 0x57000050 rtc alarm control almsec 0x57000057 0x57000054 alarm second almmin 0x5700005b 0x57000058 alarm minute almhour 0x5700005f 0x5700005c alarm hour almdate 0x57000063 0x57000060 alarm day almmon 0x57000067 0x57000064 alarm month almyear 0x5700006b 0x57000068 alarm year rtcrst 0x5700006f 0x5700006c rtc round reset bcdsec 0x57000073 0x57000070 bcd second bcdmin 0x57000077 0x57000074 bcd minute bcdhour 0x5700007b 0x57000078 bcd hour bcddate 0x5700007f 0x5700007c bcd day bcdday 0x57000083 0x57000080 bcd date bcdmon 0x57000087 0x57000084 bcd month bcdyear 0x5700008b 0x57000088 bcd year
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-40 table 1-4. S3C2440X special registers (sheet 14 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function a/d converter adccon 0x58000000 w r/w adc control adctsc 0x58000004 adc touch screen control adcdly 0x58000008 adc start or interval delay adcdat0 0x5800000c r adc conversion data adcdat1 0x58000010 adc conversion data adcupdn 0x58000014 r/w stylus up or down interrpt status spi spcon0,1 0x59000000,20 w r/w spi control spsta0,1 0x59000004,24 r spi status sppin0,1 0x59000008,28 r/w spi pin control sppre0,1 0x5900000c,2c spi baud rate prescaler sptdat0,1 0x59000010,30 spi tx data sprdat0,1 0x59000014,34 r spi rx data sd interface sdicon 0x5a000000 w r/w sdi control sdipre 0x5a000004 sdi baud rate prescaler sdicarg 0x5a000008 sdi command argument sdiccon 0x5a00000c sdi command control sdicsta 0x5a000010 r/(c) sdi command status sdirsp0 0x5a000014 r sdi response sdirsp1 0x5a000018 sdi response sdirsp2 0x5a00001c sdi response sdirsp3 0x5a000020 sdi response sdidtimer 0x5a000024 r/w sdi data / busy timer sdibsize 0x5a000028 sdi block size sdidcon 0x5a00002c sdi data control sdidcnt 0x5a000030 r sdi data remain counter sdidsta 0x5a000034 r/(c) sdi data status sdifsta 0x5a000038 r sdi fifo status sdidat 0x5a00003f 0x5a00003c b r/w sdi data sdiimsk 0x5a000040 w sdi interrupt mask
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. product overview S3C2440X 1-40 table 1-4. S3C2440X special registers (sheet of 14 of 14) register name address (b. endian) address (l. endian) acc. unit read/ write function a/d converter adccon 0x58000000 w r/w adc control adctsc 0x58000004 adc touch screen control adcdly 0x58000008 adc start or interval delay adcdat0 0x5800000c r adc conversion data adcdat1 0x58000010 adc conversion data adcupdn 0x58000014 r/w stylus up or down interrpt status spi spcon0,1 0x59000000,20 w r/w spi control spsta0,1 0x59000004,24 r spi status sppin0,1 0x59000008,28 r/w spi pin control sppre0,1 0x5900000c,2c spi baud rate prescaler sptdat0,1 0x59000010,30 spi tx data sprdat0,1 0x59000014,34 r spi rx data sd interface sdicon 0x5a000000 w r/w sdi control sdipre 0x5a000004 sdi baud rate prescaler sdicarg 0x5a000008 sdi command argument sdiccon 0x5a00000c sdi command control sdicsta 0x5a000010 r/(c) sdi command status sdirsp0 0x5a000014 r sdi response sdirsp1 0x5a000018 sdi response sdirsp2 0x5a00001c sdi response sdirsp3 0x5a000020 sdi response sdidtimer 0x5a000024 r/w sdi data / busy timer sdibsize 0x5a000028 sdi block size sdidcon 0x5a00002c sdi data control sdidcnt 0x5a000030 r sdi data remain counter sdidsta 0x5a000034 r/(c) sdi data status sdifsta 0x5a000038 r sdi fifo status sdidat 0x5a00003f 0x5a00003c b r/w sdi data sdiimsk 0x5a000040 w sdi interrupt mask
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor memory controller 5-1 5 memory controller overview the S3C2440X memory controller provides memory control signals that are required for external memory access. the S3C2440X has the following features: ? little/big endian (selectable by a software) ? address space: 128mbytes per bank (total 1gb/8 banks) ? programmable access size (8/16/32-bit) for all banks except bank0 (16/32-bit) ? total 8 memory banks six memory banks for rom, sram, etc. remaining two memory banks for rom, sram, sdram, etc . ? seven fixed memory bank start address ? one flexible memory bank start address and programmable bank size ? programmable access cycles for all memory banks ? external wait to extend the bus cycles ? supporting self-refresh and power down mode in sdram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. memory controller S3C2440X risc microprocessor 5-2 0x0000_0000 0x0800_0000 0x1000_0000 0x1800_0000 0x2000_0000 0x2800_0000 0x3000_0000 0x3800_0000 0x40000_0000 srom/sdram (ngcs7) srom/sdram (ngcs6) srom (ngcs5) srom (ngcs4) srom (ngcs3) srom (ngcs2) srom (ngcs1) boot internal sram (4kb) 128mb 128mb 128mb 128mb 128mb 128mb 2mb/4mb/8mb/16mb /32mb/64mb/128mb 2mb/4mb/8mb/16mb /32mb/64mb/128mb } refer to table 5-1 1gb haddr[29:0] accessible region srom/sdram (ngcs7) srom/sdram (ngcs6) srom (ngcs5) srom (ngcs4) srom (ngcs3) srom (ngcs2) srom (ngcs1) srom (ngcs0) om[1:0] = 01,10 om[1:0] = 00 [ not using nand flash for boot rom ] [ using nand flash for boot rom ] figure 5-1. S3C2440X memory map after reset table 5-1. bank 6/7 addresses address 2mb 4mb 8mb 16mb 32mb 64mb 128mb bank 6 start address 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 end address 0x301f_ffff 0x303f_ffff 0x307f_ffff 0x30ff_ffff 0x31ff_ffff 0x33ff_ffff 0x37ff_ffff bank 7 start address 0x3020_0000 0x3040_0000 0x3080_0000 0x3100_0000 0x3200_0000 0x3400_0000 0x3800_0000 end address 0x303f_ffff 0x307f_ffff 0x30ff_ffff 0x31ff_ffff 0x33ff_ffff 0x37ff_ffff 0x3fff_ffff note: bank 6 and 7 must have the same memory size. note: srom means rom or sram type memory
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor memory controller dec.13, 2002 5-3 function description bank0 bus width the data bus of bank0 (ngcs0) should be configured in width as one of 16-bit and 32-bit ones. because the bank0 works as the booting rom bank (map to 0x0000_0000), the bus width of bank0 should be determined before the first rom access, which will depend on the logic level of om[1:0] at reset. om1 (operating mode 1) om0 (operating mode 0) booting rom data width 0 0 nand flash mode 0 1 16-bit 1 0 32-bit 1 1 test mode memory (srom/sdram) address pin connections memory addr. pin S3C2440X addr. @ 8-bit data bus S3C2440X addr. @16-bitdatabus S3C2440X addr. @ 32-bit data bus a0 a0 a1 a2 a1 a1 a2 a3 ... ... ... ...
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. memory controller S3C2440X risc microprocessor 5-4 sdram bank address pin connection example table 5-2. sdram bank address configuration bank size bus width base component memory configuration bank address 2mbyte x8 16mbit (1m x 8 x 2bank) x 1 a20 x16 (512k x 16 x 2b) x 1 4mb x16 (1m x 8 x 2b) x 2 a21 x16 (1mx8x2b) x2 8mb x16 16mb (2m x 4 x 2b) x 4 a22 x32 (1mx8x2b) x4 x8 64mb (4m x 8 x 2b) x 1 x8 (2m x 8 x 4b) x 1 a[22:21] x16 (2m x 16 x 2b) x 1 a22 x16 (1m x 16 x 4b) x 1 a[22:21] x32 (512k x 32 x 4b) x 1 16mb x32 16mb (2mx4x2b) x8 a23 x8 64mb (8m x 4 x 2b) x 2 x8 (4m x 4 x 4b) x 2 a[23:22] x16 (4mx8x2b) x2 a23 x16 (2mx8x4b) x2 a[23:22] x32 (2m x 16 x 2b) x 2 a23 x32 (1m x 16 x 4b) x 2 a[23:22] x8 128mb (4m x 8 x 4b) x 1 x16 (2m x 16 x 4b) x 1 32mb x16 64mb (8mx4x2b) x4 a24 x16 (4mx4x4b) x4 a[24:23] x32 (4mx8x2b) x4 a24 x32 (2mx8x4b) x4 a[24:23] x16 128mb (4m x 8 x 4b) x 2 x32 (2m x 16 x 4b) x 2 x8 256mb (8m x 8 x 4b) x 1 x16 (4m x 16 x 4b) x 1 64mb x32 128mb (4m x 8 x 4b) x 4 a[25:24] x16 256mb (8m x 8 x 4b) x 2 x32 (4m x 16 x 4b) x 2 x8 512mb (16m x 8 x 4b) x 1 128mb x32 256mbit (8m x 8 x 4bank) x 4 a[26:25] x8 512mb (32m x 4 x 4b) x 2 x16 (16mx8x4b) x2 x32 (8m x 16 x 4b) x 2
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor memory controller dec.13, 2002 5-5 nwait pin operation if the wait corresponding to each memory bank is enabled, the noe duration should be prolonged by the external nwait pin while the memory bank is active. nwait is checked from tacc-1. noe will be deasserted at the next clock after sampling nwait is high. the nwe signal have the same relation with noe. trc tacs tcos tacc=4 hclk addr ngcs noe nwait data(r) delayed sampling nwait figure 5-2. S3C2440X external nwait timing diagram (tacc=4)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. memory controller S3C2440X risc microprocessor 5-6 nxbreq/nxback pin operation if nxbreq is asserted, the S3C2440X will respond by lowering nxback. if nxback=l, the address/data bus and memory control signals are in hi-z state as shown in table 1-1. when nxbreq is de-asserted, the nxback will also be de-asserted. hclk scke, a[24:0] d[31:0], ngcs noe,nwe nwbe nxbreq nxback sclk 1clk figure 5-3. S3C2440X nxbreq/nxback timing diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor memory controller dec.13, 2002 5-7 rom memory interface examples a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 d0 d1 d2 d3 d4 d5 d6 d7 nwe noe ngcsn a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce figure 5-4. memory interface with 8-bit rom a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 d0 d1 d2 d3 d4 d5 d6 d7 nwbe0 noe ngcsn a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 d8 d9 d10 d11 d12 d13 d14 d15 nwbe1 noe ngcsn a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce figure 5-5. memory interface with 8-bit rom x 2
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. memory controller S3C2440X risc microprocessor 5-8 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce d0 d1 d2 d3 d4 d5 d6 d7 nwbe0 noe ngcsn a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce d8 d9 d10 d11 d12 d13 d14 d15 nwbe1 noe ngcsn a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce d16 d17 d18 d19 d20 d21 d22 d23 nwbe2 noe ngcsn a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce d24 d25 d26 d27 d28 d29 d30 d31 nwbe3 noe ngcsn figure 5-6. memory interface with 8-bit rom x 4 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nwe noe nce nwe noe ngcsn figure 5-7. memory interface with 16-bit rom
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor memory controller dec.13, 2002 5-9 sram memory interface examples a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nwe noe ncs nwe noe ngcsn nub nlb nbe1 nbe0 figure 5-8. memory interface with 16-bit sram a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nwe noe ncs nwe noe ngcsn nub nlb nbe1 nbe0 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 d16 d17 d18 d19 d20 d21 d22 d13 d24 d25 d26 d27 d28 d29 d30 d31 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nwe noe ncs nwe noe ngcsn nub nlb nbe3 nbe2 figure 5-9. memory interface with 16-bit sram x 2
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. memory controller S3C2440X risc microprocessor 5-10 sdram memory interface examples a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ba0 ba1 ldqm udqm a21 a22 dqm0 dqm1 scke sclk scke sclk nscs0 nsras nscas nwe nscs nsras nscas nwe figure 5-10. memory interface with 16-bit sdram (4mx16, 4banks) a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ba0 ba1 ldqm udqm a22 a23 dqm0 dqm1 scke sclk scke sclk nscs0 nsras nscas nwe nscs nsras nscas nwe a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ba0 ba1 ldqm udqm a22 a23 dqm2 dqm3 scke sclk scke sclk nscs0 nsras nscas nwe nscs nsras nscas nwe d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 figure 5-11. memory interface with 16-bit sdram (4mx16 * 2ea, 4banks) note: refer to table 5-2 for the bank address configurations of sdram.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor memory controller dec.13, 2002 5-11 programmable access cycle tcoh tcos tacs hclk a[24:0] ngcs noe nwe nwbe d[31:0](r) d[31:0] (w) tacc tacp tcah tacs = 1 cycle tcos = 1 cycle tacc = 3 cycles tacp = 2 cycles tcoh = 1 cycle tcah = 2 cycles figure 5-12. S3C2440X ngcs timing diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. memory controller S3C2440X risc microprocessor 5-12 mclk scke nscs nscas addr a10/ap ra nsras ba data (cl2) data (cl3) nwe dqm trp trcd ra ca da da ba ba cb cc cd ce db dc dd de db dc dd de ba ba ba ba ba bank precharge row active write read (cl = 2, cl = 3, bl = 1) trp = 2 cycle tcas = 2 cycle trcd = 2 cycle tcp = 2 cycle figure 5-13. S3C2440X sdram timing diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor memory controller dec.13, 2002 5-13 bus width & wait control register (bwscon) register address r/w description reset value bwscon 0x48000000 r/w bus width & wait status control register 0x000000 bwscon bit description initial state st7 [31] determine sram for using ub/lb for bank 7. 0 = not using ub/lb (the pins are dedicated nwbe[3:0]) 1 = using ub/lb (the pins are dedicated nbe[3:0]) 0 ws7 [30] determine wait status for bank 7. 0 = wait disable 1 = wait enable 0 dw7 [29:28] determine data bus width for bank 7. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 0 st6 [27] determine sram for using ub/lb for bank 6. 0 = not using ub/lb (the pins are dedicated nwbe[3:0 ) 1 = using ub/lb (the pins are dedicated nbe[3:0]) 0 ws6 [26] determine wait status for bank 6. 0 = wait disable, 1 = wait enable 0 dw6 [25:24] determine data bus width for bank 6. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 0 st5 [23] determine sram for using ub/lb for bank 5. 0 = not using ub/lb (the pins are dedicated nwbe[3:0]) 1 = using ub/lb (the pins are dedicated nbe[3:0]) 0 ws5 [22] determine wait status for bank 5. 0 = wait disable, 1 = wait enable 0 dw5 [21:20] determine data bus width for bank 5. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 0 st4 [19] determine sram for using ub/lb for bank 4. 0 = not using ub/lb (the pins are dedicated nwbe[3:0]) 1 = using ub/lb (the pins are dedicated nbe[3:0]) 0 ws4 [18] determine wait status for bank 4. 0 = wait disable 1 = wait enable 0 dw4 [17:16] determine data bus width for bank 4. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 0 st3 [15] determine sram for using ub/lb for bank 3. 0 = not using ub/lb (the pins are dedicated nwbe[3:0]) 1 = using ub/lb (the pins are dedicated nbe[3:0]) 0 ws3 [14] determine wait status for bank 3. 0 = wait disable 1 = wait enable 0 dw3 [13:12] determine data bus width for bank 3. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 0 st2 [11] determine sram for using ub/lb for bank 2. 0 = not using ub/lb (the pins are dedicated nwbe[3:0]) 1 = using ub/lb (the pins are dedicated nbe[3:0].) 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. memory controller S3C2440X risc microprocessor 5-14 bus width & wait control register (bwscon) (continued) ws2 [10] determine wait status for bank 2. 0 = wait disable 1 = wait enable 0 dw2 [9:8] determine data bus width for bank 2. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 0 st1 [7] determine sram for using ub/lb for bank 1. 0 = not using ub/lb (the pins are dedicated nwbe[3:0]) 1 = using ub/lb (the pins are dedicated nbe[3:0]) 0 ws1 [6] determine wait status for bank 1. 0 = wait disable, 1 = wait enable 0 dw1 [5:4] determine data bus width for bank 1. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 0 dw0 [2:1] indicate data bus width for bank 0 (read only). 01 = 16-bit, 10 = 32-bit the states are selected by om[1:0] pins - reserved [0] reserve to 0 0 note: 1. all types of master clock in this memory controller correspond to the bus clock. for example, hclk in sram is the same as the bus clock, and sclk in sdram is also the same as the bus clock. in this chapter (memory controller), one clock means one bus clock. 2. nbe[3:0] is the 'and' signal nwbe[3:0] and noe.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor memory controller dec.13, 2002 5-15 bank control register (bankconn: ngcs0-ngcs5) register address r/w description reset value bankcon0 0x48000004 r/w bank 0 control register 0x0700 bankcon1 0x48000008 r/w bank 1 control register 0x0700 bankcon2 0x4800000c r/w bank 2 control register 0x0700 bankcon3 0x48000010 r/w bank 3 control register 0x0700 bankcon4 0x48000014 r/w bank 4 control register 0x0700 bankcon5 0x48000018 r/w bank 5 control register 0x0700 bankconn bit description initial state tacs [14:13] address set-up time before ngcsn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tcos [12:11] chip selection set-up time before noe 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tacc [10:8] access cycle 000 = 1 clock 001 = 2 clocks 010 = 3 clocks 011 = 4 clocks 100 = 6 clocks 101 = 8 clocks 110 = 10 clocks 111 = 14 clocks note: when nwait signal is used, tacc 4 clocks. 111 tcoh [7:6] chip selection hold time after noe 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 000 tcah [5:4] address hold time after ngcsn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tacp [3:2] page mode access cycle @ page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks 00 pmc [1:0] page mode configuration 00 = normal (1 data) 01 = 4 data 10 = 8 data 11 = 16 data 00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. memory controller S3C2440X risc microprocessor 5-16 bank control register (bankconn: ngcs6-ngcs7) register address r/w description reset value bankcon6 0x4800001c r/w bank 6 control register 0x18008 bankcon7 0x48000020 r/w bank 7 control register 0x18008 bankconn bit description initial state mt [16:15] determine the memory type for bank6 and bank7. 00 = rom or sram 01 = reserved (do not use) 10 = reserved (do not use) 11 = sync. dram 11 memory type = rom or sram [mt=00] (15-bit) tacs [14:13] address set-up time before ngcs 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tcos [12:11] chip selection set-up time before noe 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tacc [10:8] access cycle 000=1clock 001=2clocks 010 = 3 clocks 011 = 4 clocks 100 = 6 clocks 101 = 8 clocks 110 = 10 clocks 111 = 14 clocks 111 toch [7:6] chip selection hold time after noe 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tcah [5:4] address hold time after ngcsn 00 = 0 clock 01 = 1clock 10 = 2 clocks 11 = 4 clocks 00 tacp [3:2] page mode access cycle @ page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks 00 pmc [1:0] page mode configuration 00 = normal (1 data) 01 = 4 consecutive accesses 10 = 8 consecutive accesses 11 = 16 consecutive accesses 00 memory type = sdram [mt=11] (4-bit) trcd [3:2] ras to cas delay 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 10 scan [1:0] column address number 00 = 8-bit 01 = 9-bit 10= 10-bit 00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor memory controller dec.13, 2002 5-17 refresh control register register address r/w description reset value refresh 0x48000024 r/w sdram refresh control register 0xac0000 refresh bit description initial state refen [23] sdram refresh enable 0 = disable 1 = enable (self or cbr/auto refresh) 1 trefmd [22] sdram refresh mode 0 = cbr/auto refresh 1 = self refresh in self-refresh time, the sdram control signals are driven to the appropriate level. 0 trp [21:20] sdram ras pre-charge time 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = not support 10 trc [19:18] sdram rc minimum time 00 = 4 clocks 01 = 5 clocks 10 = 6 clocks 11 = 7 clocks 11 reserved [17:16] not used 00 reserved [15:11] not used 0000 refresh counter [10:0] sdram refresh count value. refer to chapter 6 sdram refresh controller bus priority section. refresh period = (2 11 -refresh_count+1)/hclk ex) if refresh period is 7.8 us and hclk is 100 mhz, the refresh count is as follows: refresh count = 2 11 + 1 - 100x7.8 = 1269 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. memory controller S3C2440X risc microprocessor 5-18 banksize register register address r/w description reset value banksize 0x48000028 r/w flexible bank size register 0x0 banksize bit description initial state burst_en [7] arm core burst operation enable. 0 = disable burst operation. 1 = enable burst operation. 0 reserved [6] not used 0 scke_en [5] sdram power down mode enable control by scke 0 = sdram power down mode disable 1 = sdram power down mode enable 0 sclk_en [4] sclk is enabled only during sdram access cycle for reducing power consumption. when sdram is not accessed, sclk becomes 'l' level. 0 = sclk is always active. 1 = sclk is active only during the access (recommended). 0 reserved [3] not used 0 bk76map [2:0] bank6/7 memory map 010 = 128mb/128mb 001 = 64mb/64mb 000 = 32m/32m 111 = 16m/16m 110 = 8m/8m 101 = 4m/4m 100 = 2m/2m 010
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor memory controller dec.13, 2002 5-19 sdram mode register set register (mrsr) register address r/w description reset value mrsrb6 0x4800002c r/w mode register set register bank6 xxx mrsrb7 0x48000030 r/w mode register set register bank7 xxx mrsr bit description initial state reserved [11:10] not used - wbl [9] write burst length 0: burst (fixed) 1: reserved x tm [8:7] test mode 00: mode register set (fixed) 01, 10 and 11: reserved xx cl [6:4] cas latency 000 = 1 clock, 010 = 2 clocks, 011=3 clocks others: reserved xxx bt [3] burst type 0: sequential (fixed) 1: reserved x bl [2:0] burst length 000: 1 (fixed) others: reserved xxx note: mrsr register must not be reconfigured while the code is running on sdram. important note: in sleep mode, sdram has to enter sdram self-refresh mode.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. memory controller S3C2440X risc microprocessor 5-20 notes
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-1 nand flash contorller overview in recent times , nor flash memory gets high in price while an sdram and a nand flash memory get moderate, motivating some users to execute the boot code on a nand flash and execute the main code on an sdram. S3C2440X boot code can be executed on an external nand flash memory. in order to support nand flash boot loader, the S3C2440X is equipped with an internal sram buffer called ?steppingstone?. when booting, the first 4 kbytes of the nand flash memory will be loaded into steppingstone and the boot code loaded into steppingstone will be executed. generally, the boot code will copy nand flash content to sdram. using hardware ecc, the nand flash data validity will be checked. upon the completion of the copy, the main program will be executed on the sdram. features 1) auto boot: the boot code is transferred into 4-kbytes steppingstone during reset. after the transfer, the boot code will be executed on the steppingstone. 2) nand flash memory i/f: support 256words, 512bytes, 1kwords and 2kbytes page. 3) software mode: user can directly access nand flash memory, for example this feature can be used in read/erase/program nand flash memory . 4) interface: 8 / 16-bit nand flash memory interface bus. 5) hardware ecc generation, detection and indication (software correction). 6) sfr i/f: support little endian mode, byte/half word/word access to data and ecc data register, and word access to other registers 7) steppingstone i/f: support little/big endian, byte/half word/word access. 8) the steppingstone 4-kb internal sram buffer can be used for another purpose after nand flash booting.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. n a nd fl a sh controller s3c2440 x risc microprocessor 6-2 block diagram

system bus
cle ale nfce nre nwe r/nb i/o0 - i/o15 !
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# figure 6-1 nand flash controller block diagram boot loader function

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' registers auto boot core access (boot code) user access figure 6-2 nand flash controller boot loader block diagram during reset, nand flash controller will get information about connected nand flash through pin status(ncon(adv flash), gpg13 (page size), gpg14 (address cycle), gpg15 (bus width) ? refer to pin configuration ), after power-on or system reset is occurred, the nand flash controller load automatically the 4-kbytes boot loader codes. after loading the boot loader codes, the boot loader code in steppingstone is executed. note : during the auto boot, the ecc is not checked. so, the first 4-kb of nand flash should have no bit error.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-3 pin configuration om[1:0] = 00: enable nand flash memory boot ncon : nand flash memory selection(normal / advance) 0: normal nand flash(256words/512bytes page size, 3/4 address cycle) 1: advance nand flash(1kwords/2kbytes page size, 4/5 address cycle) gpg13 : nand flash memory page capacitance selection 0: page=256words(ncon = 0) or page=1kwords(ncon = 1) 1: page=512bytes(ncon = 0) or page=2kbytes(ncon = 1) gpg14: nand flash memory address cycle selection 0: 3 address cycle(ncon = 0) or 4 address cycle(ncon = 1) 1: 4 address cycle(ncon = 0) or 5 address cycle(ncon = 1) gpg15 : nand flash memory bus width selection 0: 8-bit bus width 1: 16-bit bus width nand flash memory configuration table ncon0 gpg13 gpg14 gpg15 0: 256words 0: 3-addr 0: normal nand 1: 512bytes 1: 4-addr 0: 8-bit bus width 0: 1kwords 0: 4-addr 1: advance nand 1: 2kbytes 1: 5-addr 1: 16-bit bus width note: with above 4-bit, possible total combinations are 16, but not all the value can be used. example) nand flash configuration setting example. parts page size/total size ncon0 gpg13 gpg14] gpg15 k9s1208v0m-xxxx 512byte / 512mbit 0110 k9k2g16u0m-xxxx 1kw/2gbit1011
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. n a nd fl a sh controller s3c2440 x risc microprocessor 6-4 nand flash memory timing hclk cle / ale nwe tacls twrph0 twrph1 data command / address figure 6-3. cle & ale timing (tacls=1, twrph0=0, twrph1=0) hclk nwe / nre data data twrph0 twrph1 figure 6-4 nwe & nre timing (twrph0=0, twrph1=0)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-5 software mode S3C2440X only supports software mode access. using this mode, you can completely access the nand flash memory. the nand flash controller supports direct access interface with the nand flash memory. 1) writing to the command register = the nand flash memory command cycle 2) writing to the address register = the nand flash memory address cycle 3) writing to the data register = write data to the nand flash memory (write cycle) 4) reading from the data register = read data from the nand flash memory (read cycle) 5) reading main ecc registers and spare ecc registers = read data from the nand flash memory note : in the software mode, you have to check the rnb status input pin by using polling or interrupt.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. n a nd fl a sh controller s3c2440 x risc microprocessor 6-6 data register configuration 1) 16-bit nand flash memory interface a. word access register endian bit [31:24] bit [23:16] bit [15:8] bit [7:0] nfdata little 2 nd i/o[15:8] 2 nd i/o[ 7:0] 1 st i/o[15:8] 1 st i/o[ 7:0] nfdata big 1 st i/o[15:8] 1 st i/o[ 7:0] 2 nd i/o[15:8] 2 nd i/o[ 7:0] b. half-word access register endian bit [31:24] bit [23:16] bit [15:8] bit [7:0] nfdata little/big invalid value invalid value 1 st i/o[15:8] 1 st i/o[ 7:0] 2) 8-bit nand flash memory interface a. word access register endian bit [31:24] bit [23:16] bit [15:8] bit [7:0] nfdata little 4 th i/o[ 7:0] 3 rd i/o[ 7:0] 2 nd i/o[ 7:0] 1 st i/o[ 7:0] nfdata big 1 st i/o[ 7:0] 2 nd i/o[ 7:0] 3 rd i/o[ 7:0] 4 th i/o[ 7:0] b. half-word access register endian bit [31:24] bit [23:16] bit [15:8] bit [7:0] nfdata little invalid value invalid value 2 nd i/o[ 7:0] 1 st i/o[ 7:0] nfdata big invalid value invalid value 1 st i/o[ 7:0] 2 nd i/o[ 7:0] c. byte access register endian bit [31:24] bit [23:16] bit [15:8] bit [7:0] nfdata little/big invalid value invalid value invalid value 1 st i/o[ 7:0] steppingstone (4k-byte sram) the nand flash controller uses steppingstone as the buffer on booting and also you can use this area for another purpose.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-7 ecc(error correction code) nand flash controller has four ecc (error correction code) modules. the two ecc modules (one for data[7:0] and the other for data[15:8]) can be used for (up to) 2048 bytes ecc parity code generation, and the others(one for data[7:0] and the other for data[15:8]) can be used for (up to) 16 bytes ecc parity code generation. 28bit ecc parity code = 22bit line parity + 6bit column parity 14bit ecc parity code = 8bit line parity + 6bit column parity 2048 byte ecc parity code assignment table data7 data6 data5 data4 data3 data2 data1 data0 meccn_0 p64 p64? p32 p32? p16 p16? p8 p8? meccn_1 p1024 p1024? p512 p512? p256 p256? p128 p128? meccn_2 p4 p4? p2 p2? p1 p1? p2048 p2048? meccn_3 p8192 p8192? p4096 p4096? - - - - 16 byte ecc parity code assignment table data7 data6 data5 data4 data3 data2 data1 data0 seccn_0 p16 p16? p8 p8? p4 p4? p2 p2? seccn_1 p1 p1? p64 p64? p32 p32? - -
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. n a nd fl a sh controller s3c2440 x risc microprocessor 6-8 ecc module features ecc generation is controlled by the ecc lock (mainecclock, spareecclock) bit of the control register. ecc register configuration (little / big endian) 1) 16-bit nand flash memory interface register bit [31:24] bit [23:16] bit [15:8] bit [7:0] nfmeccd0 2 nd ecc for i/o[15:8] 2 nd ecc for i/o[7:0] 1 st ecc for i/o[15:8] 1 st ecc for i/o[7:0] nfmeccd1 4th ecc for i/o[15:8] 4 th ecc for i/o[7:0] 3 rd ecc for i/o[15:8] 3 rd ecc for i/o[7:0] register bit [31:24] bit [23:16] bit [15:8] bit [7:0] nfseccd 2 nd ecc for i/o[15:8] 2 nd ecc for i/o[7:0] 1 st ecc for i/o[15:8] 1 st ecc for i/o[7:0] 2) 8-bit nand flash memory interface register bit [31:24] bit [23:16] bit [15:8] bit [7:0] nfmeccd0 -2 nd ecc for i/o[7:0] - 1 st ecc for i/o[7:0] nfmeccd1 -4 th ecc for i/o[7:0] - 3 rd ecc for i/o[7:0] register bit [31:24] bit [23:16] bit [15:8] bit [7:0] nfseccd -2 nd ecc for i/o[7:0] - 1 st ecc for i/o[7:0] ecc programming guide 1) in software mode, ecc module generates ecc parity code for all read / write data. so you have to reset ecc value by writing the initecc(nfcont[4]) bit as ?1? and have to clear themainecclock(nfcont[5]) bit to ?0?(unlock) before read or write data. mainecclock(nfcont[5]) and spareecclock(nfcont[6]) control whether ecc parity code is generated or not. 2) whenever data is read or written, the ecc module generates ecc parity code on register nfmecc0/1. 3) after you completely read or write one page (not include spare area data), set the mainecclock bit to ?1?(lock). ecc parity code is locked and the value of the ecc status register will not be changed. 4) to generate spare area ecc parity code, clear as ?0?(unlock) spareecclock(nfcont[6]) bit. 5) whenever data is read or written, the spare area ecc module generates ecc parity code on register nfsecc. 6) after you completely read or write spare area, set the spareecclock bit to ?1?(lock). ecc parity code is locked and the value of the ecc status register will not be changed. 7) from now, you can use these values to record to the spare area or check the bit error. (note) nfseccd is for ecc in the spare area (usually, the user will write the ecc value of main data area to
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-9 spare area, which value will be the same as nfmecc0/1) and which is generated from the main data area. nand flash memory mapping not used sfr area not used bootsram (4kb) 0xffff_ffff 0x6000_0000 0x4800_0000 0x4000_0000 sfr area not used sdram (bank7, ngcs7) 0x3800_0000 sdram (bank7, ngcs7) sdram (bank6, ngcs6) 0x3000_0000 sdram (bank6, ngcs6) srom (bank5, ngcs5) srom (bank5, ngcs5) 0x2000_0000 0x2800_0000 srom (bank4, ngcs4) srom (bank3, ngcs3) srom (bank2, ngcs2) 0x1000_0000 0x1800_0000 0x0800_0000 srom (bank1, ngcs1) srom (bank4, ngcs4) srom (bank3, ngcs3) srom (bank2, ngcs2) srom (bank1, ngcs1) srom (bank0, ngcs0) bootsram (4kb) 0x0000_0000 om[1:0] = 01, 10 om[1:0] = 00 0x4000_0fff figure 6-4. nand flash memory mapping note : srom means rom or sram type memory
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. n a nd fl a sh controller s3c2440 x risc microprocessor 6-10 nand flash memory configuration i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 r/ b we ale cle ce re rnb nfwe ale cle nfce nfre data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] figure 6-1 a 8-bit nand flash memory interface i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 r/ b we ale cle ce re rn b nfwe ale cle nfce nfre data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 r/ b we ale cle ce re rn b nfwe ale cle nfce nfre data[15] data[14] data[13] data[12] data[11] data[10] data[9] data[8] figure 6-2 two 8-bit nand flash memory interface i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 r/ b we ale cle ce re i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 rn b nfwe ale cle nfce nfre data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] data[15] data[14] data[13] data[12] data[11] data[10] data[9] data[8] figure 6-3 a 16-bit nand flash memory interface
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-11 nand flash configuration register register address r/w description reset value nfconf 0x4e000000 r/w nand flash configuration register 0x0000100x nfconf bit description initial state reserved [15] reserved - tacls [14:12] cle & ale duration setting value (0~7) duration = hclk x tacls 001 reserved [11] reserved 0 twrph0 [10:8] twrph0 duration setting value (0~7) duration = hclk x ( twrph0 + 1 ) 000 reserved [7] reserved 0 twrph1 [6:4] twrph1 duration setting value (0~7) duration = hclk x ( twrph1 + 1 ) 000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. n a nd fl a sh controller s3c2440 x risc microprocessor 6-12 advflash (read only) [3] advance nand flash memory for auto-booting 0: support 256 or 512 byte/page nand flash memory 1: support 1024 or 2048 byte/page nand flash memory this bit is determined by ncon0 pin status during reset and wake-up from sleep mode. h/w set (ncon0) pagesize (read only) [2] nand flash memory page size for auto-booting advflash pagesize when advflash is 0, 0: 256 bytes/page, 1: 512 bytes/page when advflash is 1, 0: 1024 bytes/page, 1: 2048 bytes/page this bit is determined by gpg13 pin status during reset and wake-up from sleep mode. after reset, the gpg13 can be used as general i/o port or external interrupt. h/w set (gpg13) addrcycle (read only) [1] nand flash memory address cycle for auto-booting advflash addrcycle when advflash is 0, 0: 3 address cycle 1: 4 address cycle when advflash is 1, 0: 4 address cycle 1: 5 address cycle this bit is determined by gpg14pin status during reset and wake-up from sleep mode. after reset, the gpg14can be used as general i/o port or external interrupt. h/w set (gpg14) buswidth (r/w) [0] nand flash memory i/o bus width for auto-booting and general access. 0: 8-bit bus 1: 16-bit bus this bit is determined by gpg15 pin status during reset and wake-up from sleep mode. after reset, the gpg15 can be used as general i/o port or external interrupt. this bit can be changed by software. h/w set (gpg15)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-13 control register register address r/w description reset value nfcont 0x4e000004 r/w nand flash control register 0x0384 nfcont bit description initial state reserved [14:15] reserved 0 lock-tight [13] lock-tight configuration 0: disable lock-tight 1: enable lock-tight, once this bit is set to 1, you cannot clear. only reset or wake up from sleep mode can make this bit disable(can not cleared by software). when it is set to 1, the area setting in nfsblk(0x4e000038) to nfeblk(0x4e00003c)-1 is unlocked, and except this area, write or erase command will be invalid and only read command is valid. when you try to write or erase locked area, the illegal access will be occur (nfstat[3] bit will be set). if the nfsblk and nfeblk are same, entire area will be locked. 0 soft lock [12] soft lock configuration 0: disable lock 1: enable lock soft lock area can be modified at any time by software. when it is set to 1 , the area setting in nfsblk(0x4e000038) to nfeblk(0x4e00003c)-1 is unlocked, and except this area, write or erase command will be invalid and only read command is valid. when you try to write or erase locked area, the illegal access will be occur (nfstat[3] bit will be set). if the nfsblk and nfeblk are same, entire area will be locked. 1 reserved [11] reserved 0 enbillegalaccint [10] illegal access interrupt control 0: disable interrupt 1: enable interrupt illegal access interrupt is occurs when cpu tries to program or erase locking area (the area setting in nfsblk(0x4e000038) to nfeblk(0x4e00003c)-1). 0 enbrnbint [9] rnb status input signal transition interrupt control 0: disable rnb interrupt 1: enable rnb interrupt 0 rnb_transmode [8] rnb transition detection configuration 0: detect rising edge 1: detect falling edge 0 reserved [7] reserved 0 spareecclock [6] lock spare area ecc generation. 1
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. n a nd fl a sh controller s3c2440 x risc microprocessor 6-14 0: unlock spare ecc 1: lock spare ecc spare area ecc status register is nfsecc(0x4e000034), mainecclock [5] lock main data area ecc generation 0: unlock main data area ecc generation 1: lock main data area ecc generation main area ecc status register is nfmecc0/1(0x4e00002c/30), 1 initecc [4] initialize ecc decoder/encoder(write-only) 1: initialize ecc decoder/encoder 0 reserved [2:3] reserved 00 reg_nce [1] nand flash memory nfce signal control 0: force nfce to low(enable chip select) 1: force nfce to high(disable chip select) note : during boot time, it is controlled automatically. this value is only valid while mode bit is 1 1 mode [0] nand flash controller operating mode 0: nand flash controller disable (don?t work) 1: nand flash controller enable 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-15 command register register address r/w description reset value nfcmmd 0x4e000008 r/w nand flash command set register 0x00 nfcmmd bit description initial state reserved [15:8] reserved 0x00 nfcmmd [7:0] nand flash memory command value 0x00 address register register address r/w description reset value nfaddr 0x4e00000c r/w nand flash address set register 0x0000xx00 reg_addr bit description initial state reserved [15:8] reserved 0x00 nfaddr [7:0] nand flash memory address value 0x00 data register register address r/w description reset value nfdata 0x4e000010 r/w nand flash data register 0xxxxx nfdata bit description initial state nfdata [31:0] nand flash read/program data value for i/o (note) refer to data register configuration in p6-5. 0xxxxx
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. n a nd fl a sh controller s3c2440 x risc microprocessor 6-16 main data area register register address r/w description reset value nfmeccd0 0x4e000014 r/w nand flash ecc 1 st and 2 nd register for main data read (note) refer to ecc module features in p6-8. 0x00000000 nfmeccd1 0x4e000018 r/w nand flash ecc 3 rd 4 th register for main data read (note) refer to ecc module features in p6-8. 0x00000000 nfmeccd0 bit description initial state eccdata1_1 [31:24] 2 nd ecc for i/o[15:8] 0x00 eccdata1_0 [23:16] 2 nd ecc for i/o[ 7:0] note : in software mode, read this register when you need to read 2 nd ecc value from nand flash memory 0x00 eccdata0_1 [15:8] 1 st ecc for i/o[15:8] 0x00 eccdata0_0 [7:0] 1 st ecc for i/o[ 7:0] note : in software mode, read this register when you need to read 1 st ecc value from nand flash memory. this register has same read function of nfdata. 0x00 (note) only word access is valid. nfmeccd1 bit description initial state eccdata3_1 [31:24] 4 th ecc for i/o[15:8] 0x00 eccdata3_0 [23:16] 4 th ecc for i/o[ 7:0] note : in software mode, read this register when you need to read 4 th ecc value from nand flash memory 0x00 eccdata2_1 [15:8] 3 rd ecc for i/o[15:8] 0x00 eccdata2_0 [7:0] 3 rd ecc for i/o[ 7:0] note: in software mode, read this register when you need to read 3 rd ecc value from nand flash memory. this register has same read function of nfdata. 0x00 (note) only word access is valid. important note main data area register (nfmeccd0/1) does not meet the specification. next revision chip will meet the specification. workaround: ecc detection by software
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-17 spare area ecc register register address r/w description reset value nfseccd 0x4e00001c r/w n a nd flash ecc(e r r o r co r r ection code) r egiste r fo r spa r e area data read 0x00000000 nfseccd bit description initial state eccdata1_1 [31:24] 2 nd ecc for i/o[15:8] 0x00 eccdata1_0 [23:16] 2 nd ecc for i/o[ 7:0] note: in software mode, read this register when you need to read 2 nd ecc value from nand flash memory 0x00 eccdata0_1 [15:8] 1 st ecc for i/o[15:8] 0x00 eccdata0_0 [7:0] 1 st ecc for i/o[ 7:0] note: in software mode, read this register when you need to read 1 st ecc value from nand flash memory. this register has same read function of nfdata. 0x00 (note) only word access is valid.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. n a nd fl a sh controller s3c2440 x risc microprocessor 6-18 nfcon status register register address r/w description reset value nfstat 0x4e000020 r/w nand flash operation status register 0xxx00 nfstat bit description initial state reserved [7] reserved x reserved [4:6] reserved 0 illegalaccess [3] once soft lock or lock-tight is enabled, the illegal access (program, erase) to the memory makes this bit set. 0: illegal access is not detected 1: illegal access is detected 0 rnb_transdetect [2] when rnb low to high transition is occurred, this value set and issue interrupt if enabled. to clear this value write ?1?. 0: rnb transition is not detected 1: rnb transition is detected transition configuration is set in rnb_transmode(nfcont[8]). 0 nce (read-only) [1] the status of nce output pin 1 rnb (read-only) [0] the status of rnb input pin. 0: nand flash memory busy 1: nand flash memory ready to operate 1
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-19 ecc0/1 status register register address r/w description reset value nfestat0 0x4e000024 r/w nand flash ecc status register for i/o [7:0] 0x00000000 nfestat1 0x4e000028 r/w nand flash ecc status register for i/o [15:8] 0x00000000 nfestat0 bit description initial state serrordatano [24:21] in spare area, indicates which number data is error 00 serrorbitno [20:18] in spare area, indicates which bit is error 000 merrordatano [17:7] in main data area, indicates which number data is error 0x00 merrorbitno [6:4] in main data area, indicates which bit is error 000 spareerror [3:2] indicates whether spare area bit fail error occurred 00: no error 01: 1-bit error(correctable) 10: multiple error 11: ecc area error 00 mainerror [1:0] indicates whether main data area bit fail error occurred 00: no error 01: 1-bit error(correctable) 10: multiple error 11: ecc area error 00 note : the above value s are only valid when both ecc register and ecc status register have valid value. nfestat1 bit description initial state serrordatano [24:21] in spare area, indicates which number data is error 00 serrorbitno [20:18] in spare area, indicates which bit is error 000 merrordatano [17:7] in main data area, indicates which number data is error 0x00 merrorbitno [6:4] in main data area, indicates which bit is error 000 spareerror [3:2] indicates whether spare area bit fail error occurred 00: no error 01: 1-bit error(correctable) 10: multiple error 11: ecc area error 00 mainerror [1:0] indicates whether main data area bit fail error occurred 00: no error 01: 1-bit error(correctable) 10: multiple error 11: ecc area error 00 note : the above value s are only valid when both ecc register and ecc status register have valid value.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. n a nd fl a sh controller s3c2440 x risc microprocessor 6-20 main data area ecc0 status register register address r/w description reset value nfmecc0 0x4e00002c r nand flash ecc register for data[7:0] 0xxxxxxx nfmecc1 0x4e000030 r nand flash ecc register for data[15:8] 0xxxxxxx nfmecc0 bit description initial state mecc0_3 [31:24] ecc3 for data[7:0] 0xxx mecc0_2 [23:16] ecc2 for data[7:0] 0xxx mecc0_1 [15:8] ecc1 for data[7:0] 0xxx mecc0_0 [7:0] ecc0 for data[7:0] 0xxx nfmecc1 bit description initial state mecc1_3 [31:24] ecc3 data[15:8] 0xxx mecc1_2 [23:16] ecc2 data[15:8] 0xxx mecc1_1 [15:8] ecc1 data[15:8] 0xxx mecc1_0 [7:0] ecc0 data[15:8] 0xxx (note) the nand flash controller generate nfmecc0/1 when read or write main area data while the mainecclock(nfcont[5]) bit is ?0?(unlock). spare area ecc status register register address r/w description reset value nfsecc 0x4e000034 r nand flash ecc register for i/o [15:0] 0xxxxxxx nfsecc bit description initial state secc1_1 [31:24] spare area ecc1 status for i/o[15:8] 0xxx secc1_0 [23:16] spare area ecc0 status for i/o[15:8] 0xxx secc0_1 [15:8] spare area ecc1 status for i/o[7:0] 0xxx secc0_0 [7:0] spare area ecc0 status for i/o[7:0] 0xxx (note) the nand flash controller generate nfsecc when read or write spare area data while the spareecclock(nfcont[6]) bit is ?0?(unlock).
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor n a nd fl a sh controller 6-21 block address register register address r/w description reset value nfsblk 0x4e000038 r/w nand flash programmable start block address 0x000000 nfeblk 0x4e00003c r/w nand flash programmable end block address nand flash can be p r og r ammed between sta r tandend address. when the soft lock or lock-tight is enabled and the sta r t and end add r ess has same value, enti r ea r ea of n a nd flash will be locked. 0x000000 nfsblk bit description initial state sblk_addr2 [23:16] the 3 rd block address of the block erase operation 0x00 sblk_addr1 [15:8] the 2 nd block address of the block erase operation 0x00 sblk_addr0 [7:0] the 1 st block address of the block erase operation (only bit [7:5] are valid) 0x00 note : advance flash?s block address start from 3-address cycle. so block address register only needs 3-bytes . nfeblk bit description initial state eblk_addr2 [23:16] the 3 rd block address of the block erase operation 0x00 eblk_addr1 [15:8] the 2 nd block address of the block erase operation 0x00 eblk_addr0 [7:0] the 1 st block address of the block erase operation (only bit [7:5] are valid) 0x00 note : advance flash?s block address start from 3-address cycle. so block address register only needs 3-bytes . the nfslk and nfeblk can be changed while soft lock bit(nfcont[12]) is enabled. but cannot be changed when lock-tight bit(nfcont[13]) is set. when lock-tight =1 or softlock=1 nand flash memory locked area (read only) prorammable/ readable area locked area (read only) nfsblk address high low nfeblk nfeblk-1 nfsblk nfeblk locked area (read only) when nfsblk=nfeblk
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor clock & power management 7 - 1 clock & power management overview the clock & power management block consists of three parts: c lock control, usb control, and p ower control. the clock control logic in S3C2440X can generate the required clock signals including fclk for cpu, hclk for the ahb bus peripherals, and pclk for the apb bus peripherals. the S3C2440X has two phase locked loops (plls): one for fclk, hclk, and pclk, and the other dedicated for usb block (48mhz). the clock control logic can make slow clocks without pll and connect/disconnect the clock to each peripheral block by software, which will reduce the power consumption. for the power control logic, the S3C2440X has various power management schemes to keep optimal power consumption for a given task. the power management block in the S3C2440X can activate four modes: normal mode, slow mode, idle mode, and sleep mode. normal mode : the block supplies clocks to cpu as well as all peripherals in the S3C2440X. in this mode, the power consumption will be maximized when all peripherals are turned on. it allows the user to control the operation of peripherals by software. for example, if a timer is not needed, the user can disconnect the clock to the timer to reduce power consumption. slow mode : non-pll mode. unlike the normal mode, the slow mode uses an external clock (xtipll or extclk) directly as fclk in the S3C2440X without pll. in this mode, the power consumption depends on the frequency of the external clock only. the power consumption due to pll is excluded. idle mode : the block disconnects clocks (fclk) only to the cpu core while it supplies clocks to all other peripherals. the idle mode results in reduced power consumption due to cpu core. any interrupt request to cpu can be woken up from the idle mode. sleep mode : the block disconnects the internal power. so, there occurs no power consumption due to cpu and the internal logic except the wake-up logic in this mode. activating the sleep mode requires two independent power sources. one of the two power sources supplies the power for the wake-up logic. the other one supplies other internal logics including cpu, and should be controlled for power on/off. in the sleep mode, the second power supply source for the cpu and internal logics will be turned off. the wakeup from sleep mode can be issued by the eint[15:0] or by rtc alarm interrupt.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 2 functional description clock architecture figure 7-1 shows a block diagram of the clock architecture. the main clock source comes from an external crystal (xtipll) or an external clock (extclk). the clock generator includes an oscillator (oscillation amplifier), which is connected to an external crystal, and also has two plls (phase-locked-loop), which generate the high frequency clock required in the S3C2440X. clock source selection table 7-1 shows the relationship between the combination of mode control pins (om3 and om2) and the selection of source clock for the S3C2440X. the om[3:2] status is latched internally by referring the om3 and om2 pins at therisingedgeofnreset. table 7-1. clock source selection at boot-up mode om[3:2] mpll state upll state main clock source usb clock source 00 on on crystal crystal 01 on on crystal extclk 10 on on extclk crystal 11 on on extclk extclk note: 1. although the mpll starts just after a reset, the mpll output (mpll) is not used as the system clock until the software writes valid settings to the mpllcon register. before this valid setting, the clock from external crystal or extclk source will be used as the system clock directly. even if the user does not want to change the default value of mpllcon register, the user should write the same value into mpllcon register. 2. om[3:2] is used to determine a test mode when om[1:0] is 11.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 3 nand flash controller osc mpll upll clkcntl fclk hdivn pdivn mpll control signal upll powcntl fh p usbcntl test mode om[1:0] bus controller memory controller arbitration dma 4ch wdt i 2 s sdi adc uart(0,1,2) pwm i 2 c gpio rtc spi(0,1) usb device arm920t interrupt controller lcd controller h_lcd p_sdi p_gpio p_adc p_rtc p_uart p_spi p_i 2 s p_i 2 c p_pwm p_usb h_nand fclk pclk hclk uclk power management block mpll clk upll clk hclk pclk fclk clkout xtipll xtopll extclk p[5:0] m[7:0] s[1:0] om[3:2] p[5:0] m[7:0] s[1:0] usb host i/f h_usb tic h_cam cam extmater divn_upll 1/1 or 1/2 camdivn figure 7-1. clock generator block diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 4 phase locked loop (pll) the mpll within the clock generator, as a circuit, synchronizes an output signal with a reference input signal in frequency and phase. in this application, it includes the following basic blocks as shown in figure 7-2: the voltage controlled oscillator (vco) to generate the output frequency proportional to input dc voltage, the divider p to divide the input frequency (fin) by p, the divider m to divide the vco output frequency by m which is input to phase frequency detector (pfd), the divider s to divide the vco output frequency by s which is mpll (the output frequency from mpll block), the phase difference detector, the charge pump, and the loop filter. the output clock frequency mpll is related to the reference input clock frequency fin by the following equation: mpll = (m * fin) / (p * 2 s ) m = m (the value for divider m)+ 8, p = p (the value for divider p) + 2 the upll within the clock generator is the same as the mpll in every aspect. the following sections describes the operation of the pll, including the phase difference detector, the charge pump, the voltage controlled oscillator (vco), and the loop filter. phase difference detector (pfd) the pfd monitors the phase difference between fref and fvco, and generates a control signal (tracking signal) when thedifferenceisdetected . the fref means the reference frequency as shown in the figure 7-2. charge pump (pump) the charge pump converts pfd control signals into a proportional charge in voltage across the external filter that drives the vco. loop filter the control signal, which the pfd generates for the charge pump, may generate large excursions (ripples) each time the fvco is compared to the fref. to avoid overloading the vco, a low pass filter samples and filters the high-frequency components out of the control signal. the filter is typically a single-pole rc filter with a resistor and a capacitor. voltage controlled oscillator (vco) the output voltage from the loop filter drives the vco, causing its oscillation frequency to increase or decrease linearly as a function of variations in average voltage. when the fvco matches fref in terms of frequency as well as phase, the pfd stops sending control signals to the charge pump, which in turn stabilizes the input voltage to the loop filter. the vco frequency then remains constant, and the pll remains fixed onto the system clock. usual conditions for pll & clock generator pll & clock generator generally uses the following conditions. mpllcap: 2.8 nf loop filter capacitance c lf upllcap: 700 pf external x-tal frequency - 10?20mhz (note) external capacitance used for x-tal c ext 15?22pf notes: 1. the value could be changed. 2. fclk must be more than three times x-tal or extclk (fclk 3x-tal or 3extclk)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 5 divider p loop filter fin m[7:0] s[1:0] pfd divider m p[5:0] f vco pump vco divider s f ref mpll,upll r c internal c lf external mpllcap, upllcap figure 7-2. pll (phase-locked loop) block diagram extclk xtipll xtopll extclk xtipll xtopll external osc a) x-tal oscillation (om[3:2]=00) b) external clock source (om[3:2]=11) v dd v dd c ext c ext figure 7-3. main oscillator circuit examples
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 6 clock control logic the clock control logic determines the clock source to be used, i.e., the pll clock (mpll) or the direct external clock (xtipll or extclk). when pll is configured to a new frequency value, the clock control logic disables the fclk until the pll output is stabilized using the pll locking time. the clock control logic is also activated at power-on reset and wakeup from power-down mode. power-on reset (xtipll) figure 7-4 shows the clock behavior during the power-on reset sequence. the crystal oscillator begins oscillation within several milliseconds. when nreset is released after the stabilization of osc (xtipll) clock, the pll starts to operate according to the default pll configuration. however, pll is commonly known to be unstable after power-on reset, so fin is fed directly to fclk instead of the mpll (pll output) before the software newly configures the pllcon. even if the user does not want to change the default value of pllcon register after reset, the user should write the same value into pllcon register by software. the pll restarts the lockup sequence toward the new frequency only after the software configures the pll with a new frequency. fclk can be configured as pll output (mpll) immediately after lock time. the logic operates by xtipll nreset osc (xtipll) vco output power clock disable lock time pll is configured by s/w first time. vco is adapted to new clock frequency. fclk fclk is new frequency pll can operate after om[3:2] is latched. figure 7-4. power-on reset sequence (when the external clock source is a crystal oscillator)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 7 change pll settings in normal operation mode during the operation of the S3C2440X in normal mode, the user can change the frequency by writing the pms value and the pll lock time will be automatically inserted. during the lock time, the clock is not supplied to the internal blocks in the S3C2440X. figure 7-5 shows the timing diagram. mpll pms setting pll lock-time fclk it changes to new pll clock after automatic lock time. figure 7-5. changing slow clock by setting pms value usb clock control usb host interface and usb device interface needs 48mhz clock. in the S3C2440X, the usb dedicated pll (upll) generates 48mhz for usb. uclk does not fed until the pll (upll) is configured. condition uclk state upll state after reset xtlpll or extclk on after configuring upll l : during pll lock time 48mhz: after pll lock time on upll is turned off by clkslow register xtlpll or extclk off upll is turned on by clkslow register 48mhz on
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 8 fclk, hclk, and pclk fclk is used by arm920t. hclk is used for ahb bus, which is used by the arm920t, the memory controller, the interrupt controller, the lcd controller, the dma and usb host block. pclk is used for apb bus, which is used by the peripherals such as wdt, iis, i2c, pwm timer, mmc interface, adc, uart, gpio, rtc and spi. the S3C2440X supports selection of dividing ratio between fclk, hlck and pclk. this ratio is determined by hdivn and pdivn of clkdivn control register. hdivn pdivn fclk hclk pclk divide ratio 0 0 fclk fclk fclk 1 : 1 : 1 (default) 0 1 fclk fclk fclk / 2 1 : 1 : 2 1 0 fclk fclk / 2 fclk / 2 1 : 2 : 2 1 1 fclk fclk / 2 fclk / 4 1 : 2 : 4 3 0 fclk fclk / 3 fclk / 3 1 : 3 : 3 3 1 fclk fclk / 3 fclk / 6 1 : 3 : 6 2 0 fclk fclk / 4 fclk / 4 1 : 4 : 4 2 1 fclk fclk / 4 fclk / 8 1 : 4 : 8 after setting pms value, it is required to set clkdivn register. the value set for clkdivn will be valid after pll lock time. the value is also available for reset and changing power management mode. the setting value can also be valid after 1.5 hclk. only, 1hclk can validate the value of clkdivn register changed from default (1:1:1) to other divide ratio (1:1:2, 1:2:2 and 1:2:4) 1hclk 1.5 hclk 1.5 hclk 0x00000000 0x00000001(1:1:2) 0x00000003 (1:2:4) 0x00000000 (1:1:1) clkdivn fclk hclk pclk figure 7-6. changing clkdivn register value
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 9 note 1. clkdivn should be set carefully not to exceed the limit of hclk and pclk. 2. if hdivn is not 0, the cpu bus mode has to be changed from the fast bus mode to the asynchronous bus mode using following instructions. mmu_setasyncbusmode mrc p15,0,r0,c1,c0,0 orr r0,r0,#r1_nf:or:r1_ia mcr p15,0,r0,c1,c0,0 if hdivn is not 0 and the cpu bus mode is the fast bus mode, the cpu will operate by the hclk. this feature can be used to change the cpu frequency as a half or more without affecting the hclk and pclk.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 10 power management the p ower m anagement block controls the system clocks by software for the reduction of power consumption in the S3C2440X. these schemes are related to pll, clock control logics (fclk, hclk, and pclk) and wakeup signals. figure 7-7 shows the clock distribution of the S3C2440X. the S3C2440X has four power modes. the following section describes each power management mode. the transition between the modes is not allowed freely. please see figure 7-8 for available transitions among the modes. intcntl power management fclk input clock fclk defination if slow mode fclk = input clock/divider ratio if normal mode (p, m & s value) fclk = mpll clock (mpll) arm920t hclk pclk upll(96/48 mhz) buscntl memcntl arb/dma extmaster lcdcntl nand flash controller camera wdt spi pwm i2c sdi adc uart i2s gpio rtc usb device clock control register usb host i/f 1/d 1/2 1/1 figure 7-7. the clock distribution block diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 11 idle sleep normal (slow_bit=0) slow (slow_bit=1) idle_bit=1 interrupts, eint[0:23], rtc alarm sleep bit=1 eint[15:0], rtc alarm reset figure 7-8. power management state diagram table 7-2. clock and power state in each power mode mode arm920t ahb modules (1) /wdt power management gpio 32.768khz rtc clock apb modules (2) & usbh/lcd/nand normal o o o sel o sel idle x o o sel o sel slow o o o sel o sel sleep off off wait for wake- up event previous state ooff notes: 1. usb host,lcd, and nand are excluded. 2. wdt is excluded. rtc interface for cpu access is included. 3. sel : selectable(o,x), o : enable , x : disable off: power is turned off
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 12 normal mode in n ormal mode, all peripherals and the basic blocks including power management block, the cpu core, the bus controller, the memory controller, the interrupt controller, dma, and the external master may operate fully. but, the clock to each peripheral, except the basic blocks, can be stopped selectively by software to reduce the power consumption. idle mode in idle mode, the clock to the cpu core is stopped except the bus controller, the memory controller, the interrupt controller, and the power management block. to exit the idle mode, eint[23:0], or rtc alarm interrupt, or the other interrupts should be activated. (eint is not available until gpio block is turned on). slow mode (non-pll mode) power consumption can be reduced in the slow mode by applying a slow clock and excluding the power consumption from the pll. the fclk is the frequency of divide_by_n of the input clock (xtipll or extclk) without pll. the divider ratio is determined by slow_val in the clkslow control register and clkdivn control register. table 7-3. clkslow and clkdivn register settings for slow clock example slow_val fclk hclk pclk uclk 1/1 option (hdivn=0) 1/2 option (hdivn=1) 1/1 option (pdivn=0) 1/2 option (pdivn=1) 0 0 0 extclk or xtipll / 1 extclk or xtipll / 1 extclk or xtipll / 2 hclk hclk / 2 48 mhz 0 0 1 extclk or xtipll / 2 extclk or xtipll / 2 extclk or xtipll / 4 hclk hclk / 2 48 mhz 0 1 0 extclk or xtipll / 4 extclk or xtipll / 4 extclk or xtipll / 8 hclk hclk / 2 48 mhz 0 1 1 extclk or xtipll / 6 extclk or xtipll / 6 extclk or xtipll / 12 hclk hclk / 2 48 mhz 1 0 0 extclk or xtipll / 8 extclk or xtipll / 8 extclk or xtipll / 16 hclk hclk / 2 48 mhz 1 0 1 extclk or xtipll / 10 extclk or xtipll / 10 extclk or xtipll / 20 hclk hclk / 2 48 mhz 1 1 0 extclk or xtipll / 12 extclk or xtipll / 12 extclk or xtipll / 24 hclk hclk / 2 48 mhz 1 1 1 extclk or xtipll / 14 extclk or xtipll / 14 extclk or xtipll / 28 hclk hclk / 2 48 mhz in slow mode, pll will be turned off to reduce the pll power consumption. when the pll is turned off in the slow mode and the user changes power mode from slow mode to normal mode, the pll needs clock stabilization time (pll lock time). this pll stabilization time is automatically inserted by the internal logic with lock time count register. the pll stability time will take 300us after the pll is turned on. during pll lock time, the fclk becomes slow clock.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 13 users can change the frequency by enabling slow mode bit in clkslow register in pll on state. the slow clock is generated during the slow mode. figure 7-11 shows the timing diagram. mpll slow mode disable fclk slow mode enable slow_bit divided external clock mpll_off it changes to pll clock after slow mode off figure 7-9. issuing exit_from_slow_mode command in pll on state if the user switches from slow mode to normal mode by disabling the slow_bit in the clkslow register after pll lock time, the frequency is changed just after slow mode is disabled. figure 7-12 shows the timing diagram. mpll fclk slow_bit divided osc clock mpll_off software lock time slow mode disable pll off pll on slow mode enable it changes to pll clock after slow mode off figure 7-10. issuing exit_from_slow_mode command after lock time
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 14 if the user switches from slow mode to normal mode by disabling slow_bit and mpll_off bit simultaneously in the clkslow register, the frequency is changed just after the pll lock time. figure 7-13 shows the timing diagram. mpll fclk slow_bit divided osc clock mpll_off hardware lock time pll off pll on slow mode enable it changes to pll clock after lock time automatically slow mode disable figure 7-11. issuing exit_from_slow_mode command and the instant pll_on command simultaneously
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 15 sleep mode the block disconnects the internal power. so, there occurs no power consumption due to cpu and the internal logic except the wake-up logic in this mode. activating the sleep mode requires two independent power sources. one of the two power sources supplies the power for the wake-up logic. the other one supplies other internal logics including cpu, and should be controlled for power on/off. in the sleep mode, the second power supply source for the cpu and internal logics will be turned off. the wakeup from sleep mode can be issued by the eint[15:0] or by rtc alarm interrupt. follow the procedure to enter sleep mode 1. set the gpio configuration adequate for sleep mode. 2. mask all interrupts in the intmsk register. 3. configure the wake-up sources properly including rtc alarm. (the bit of eintmask corresponding to the wake-up source has not to be masked in order to let the corresponding bit of srcpnd or eintpend set. although a wake-up source is issued and the corresponding bit of eintmask is masked, the wake-up will occur and the corresponding bit of srcpnd or eintpend will not be set.) 4. set usb pads as suspend mode. (misccr[13:12]=11b) 5. save some meaning values into gstatus[4:3] register. these register are preserved during sleep mode. 6. configure misccr[1:0] for the pull-up resisters on the data bus,d[31:0]. if there is an external bus holder, such as 74lvch162245, turn off the pull-up resistors. if not, turn on the pull-up resistors. additionally, the memory concerning pins are set to two type, one is hi-z, and the other is inactive state. 7. stop lcd by clearing lcdcon1.envid bit. 8. read rrefresh and rclkcon registers in order to fill the tlb. 9. let sdram enter the self-refresh mode by setting the refresh[22]=1b. 10. wait until sdram self-refresh is effective. 11. set misccr[19:17]=111b to make sdram signals(sclk0,sclk1 and scke) protected during sleep mode 12. set the sleep mode bit in the clkcon register.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 16 follow the procedure to wake-up from sleep mode 1. the internal reset signal will be asserted if one of the wake-up sources is issued. it?s exactly same with the case of the assertion of the external nreset pin. this reset duration is determined by the internal 16-bit counter logic and the reset assertion time is calculated as trst = (65535 / xtal_frequency). 2. check gstatus2[2] in order to know whether or not the power-up is caused by the wake-up from sleep mode. 3. release the sdram signal protection by setting misccr[19:17]=000b. 4. configure the sdram memory controller. 5. wait until the sdram self-refresh is released. mostly sdram needs the refresh cycle of all sdram row. 6. the information in gstatus[3:4] can be used for user?s own purpose because the value in gstatus[3:4] has been preserved during sleep mode. 7. ? for eint[3:0], check the srcpnd register. ? for eint[15:4], check the eintpend instead of srcpnd (srcpnd will not be set although some bits of eintpend are set.). ? for alarm wake-up, check the rtc time because the rtc bit of srcpnd isn?t set at the alarm wake-up. ? if there was the nbatt_flt assertion during sleep mode, the corresponding bit of srcpnd has been set. pin states in sleep mode the pin state of the sleep mode is as follows; pin type pin example pin states in sleep mode gpio output pin gpb0:input output ( gpio data register value is used.) gpio input pin gpb0:output input gpio bi-directional pin gpg6:spimosi input function output pin ngcs0 output (the last output level is held.) function input pin nwait input
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 17 power control of vddi and vddiarm in sleep mode, only vddi and vddiarm will be turned off, which is controlled by pwren pin. if pwren signal is active(h), vddi and vddiarm are supplied by an external voltage regulator. if pwren pin is inactive (l), the vddi and vddiarm are turned off. note although vddi and vddiarm may be turned off, the other power pins have to be supplied. S3C2440X power ctrl (alive block) rtc alarm eint external interrupt 3.3v power pwren vddi vddiarm vddmpll vddupll core & peripherals rtc i/o 1.2v regulator 1.2v en 1.2v power vddalive figure 7-12. sleep mode
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 18 signaling eint[15:0] for wakeup the S3C2440X can be woken up from sleep mode only if the following conditions are met. a) level signals (h or l) or edge signals (rising or falling or both) are asserted on eintn input pin. b) the eintn pin has to be configured as eint in the gpio control register. c) nbatt_flt pin has to be h level. it is important to configure the eintn in the gpio control register as an external interrupt pins, considering the condition a) above. just after the wake-up, the corresponding eintn pin will not be used for wakeup. this means that the pin can be used as an external interrupt request pin again. entering idle mode if clkcon[2] is set to 1 to enter the idle mode, the S3C2440X will enter idle mode after some delay (until the power control logic receives ack signal from the cpu wrapper). pll on/off the pll can only be turned off for low power consumption in slow mode. if the pll is turned off in any other mode, mcu operation is not guaranteed. when the processor is in slow mode and tries to change its state into other state with the pll turned on, then slow_bit should be clear to move to another state after pll stabilization pull-up resistors on the data bus and sleep mode in sleep mode, the data bus (d[31:0] or d[15:0] ) is in hi-z state. but, because of the characteristics of i/o pad, the data bus pull-up resistors have to be turned on for low power consumption in sleep mode. d[31:0] pin pull-up resistors can be controlled by the gpio control register (misccr). however, if there is an external bus holder, such as 74lvch162245, on the data bus, turning off the data bus pull-up resistors will be reduce power consumption.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 19 output port state and sleep mode if output is l, the current will be consumed through the internal parasitic resistance; if the output is h, the current will not be consumed. for an output port, the current consumption can be reduced if the output state is h. it is recommended that the output ports be in h state to reduce current consumption in sleep mode. battery fault signal(nbatt_flt) there are two functions in nbatt_flt pin as follows; ? when cpu is not in sleep mode, nbatt_flt pin will cause the interrupt request. the interrupt attribute of the nbatt_flt is l-level triggered. ? while cpu is in sleep mode, assertion of the nbatt_flt will prohibit the wake up from the power-down mode. so, any wake-up source will be masked if nbatt_flt is asserted, which is protecting the system malfunction of the low battery capacity adc power down the adc has an additional power-down bit in adccon. if the S3C2440X enters the sleep mode, the adc should enter its own power-down mode.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 20 clock generator & power management special register lock time count register (locktime) register address r/w description reset value locktime 0x4c000000 r/w pll lock time count register 0xffffffff locktime bit description initial state u_ltime [31:16] upll lock time count value for uclk. (u_ltime ? 300us) 0xffff m_ltime [15:0] mpll lock time count value for fclk, hclk, and pclk (m_ltime ? 300us) 0xffff pll control register (mpllcon and upllcon) mpll = (m * fin) / (p * 2 s ) m=(mdiv+8),p=(pdiv+2),s=sdiv pll value selection guide (mpllcon) 1. f out =m*fin/(p*2 s ), f vco = m * fin / p where : m=mdiv+8, p=pdiv+2, s=sdiv 2. 200mhz f vco 500mhz 3. 100mhz f out 500mhz (the max. f out of the pll itself is 500mhz) 4. fclk 3x-tal or 3extclk note: although there is the rule for choosing pll value, we recommend only the values in the pll value recommendation table. if you have to use another value, please contact us. register address r/w description reset value mpllcon 0x4c000004 r/w mpll configuration register 0x00096030 upllcon 0x4c000008 r/w upll configuration register 0x0004d030 pllcon bit description initial state mdiv [19:12] main divider control 0x96 / 0x4d pdiv [9:4] pre-divider control 0x03 / 0x03 sdiv [1:0] post divider control 0x0 / 0x0 note: when you set mpll&upll values simultaneously, set mpll value first and then upll value.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 21 pll value selection table it is not easy to find a proper pll value. so, we recommend referring to the following pll value recommendation table. input frequency output frequency mdiv pdiv sdiv 12.00mhz 48.00 mhz (note) 56(0x38) 2 2 12.00mhz 96.00 mhz (note) 56(0x38) 2 1 12.00mhz 101.60 mhz 246(0xf6) 13(0xd) 1 12.00mhz 112.909 mhz 199(0xc7) 9 1 12.00mhz 118.50 mhz 150(0x96) 6 1 12.00mhz 124.20 mhz 199(0xc7) 8 1 12.00mhz 135.429 mhz 150(0x96) 5 1 12.00mhz 146.667 mhz 212(0xd4) 7 1 12.00mhz 152.400 mhz 119(0x77) 3 1 12.00mhz 158.00 mhz 71(0x47) 1 1 12.00mhz 169.333 mhz 246(0xf6) 7 1 12.00mhz 180.750 mhz 233(0xe9) 6 1 12.00mhz 186.00 mhz 85(0x55) 1 1 12.00mhz 192.00 mhz 88(0x58) 1 1 12.00mhz 203.20 mhz 246(0xf6) 13(0xd) 0 12.00mhz 214.50 mhz 135(0x87) 2 1 12.00mhz 220.286 mhz 249(0xf9) 12(0xc) 0 12.00mhz 225.818 mhz 199(0xc7) 9 0 12.00mhz 237.00 mhz 150(0x96) 6 0 12.00mhz 248.40 mhz 199(0xc7) 8 0 12.00mhz 254.00 mhz 119(0x77) 4 0 12.00mhz 259.636 mhz 230(0xe6) 9 0 12.00mhz 270.857 mhz 150(0x96) 5 0 12.00mhz 282.00 mhz 86(0x56) 2 0 12.00mhz 288.00 mhz 64(0x40) 1 0 12.00mhz 293.333 mhz 212(0xd4) 7 0 12.00mhz 304.80 mhz 119(0x77) 3 0 12.00mhz 316.00 mhz 71(0x47) 1 0 12.00mhz 321.60 mhz 126(0x7e) 3 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 22 pll value selection table ( continued) input frequency output frequency mdiv pdiv sdiv 12.00mhz 327.429 mhz 183(0xb7) 5 0 12.00mhz 338.667 mhz 246(0xf6) 7 0 12.00mhz 350.00 mhz 167(0xa7) 4 0 12.00mhz 355.50 mhz 229(0xe5) 6 0 12.00mhz 361.50 mhz 233(0xe9) 6 0 12.00mhz 372.00 mhz 85(0x55) 1 0 12.00mhz 384.00 mhz 88(0x58) 1 0 12.00mhz 389.143 mhz 219(0xdb) 5 0 12.00mhz 400.00 mhz 92(0x5c) 1 0 note: the 48.00mhz and 96mhz output is used for upllcon register.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 23 clock control register (clkcon) register address r/w description reset value clkcon 0x4c00000c r/w clock generator control register 0xffff0 clkcon bit description initial state camera [19] control hclk into camera block. 0 = disable, 1 = enable 1 spi [18] control pclk into spi block. 0 = disable, 1 = enable 1 iis [17] control pclk into iis block. 0 = disable, 1 = enable 1 iic [16] control pclk into iic block. 0 = disable, 1 = enable 1 adc(&touch screen) [15] control pclk into adc block. 0 = disable, 1 = enable 1 rtc [14] control pclk into rtc control block. even if this bit is cleared to 0, rtc timer is alive. 0 = disable, 1 = enable 1 gpio [13] control pclk into gpio block. 0 = disable, 1 = enable 1 uart2 [12] control pclk into uart2 block. 0 = disable, 1 = enable 1 uart1 [11] control pclk into uart1 block. 0 = disable, 1 = enable 1 uart0 [10] control pclk into uart0 block. 0 = disable, 1 = enable 1 sdi [9] control pclk into sdi interface block. 0 = disable, 1 = enable 1 pwmtimer [8] control pclk into pwmtimer block. 0 = disable, 1 = enable 1 usb device [7] control pclk into usb device block. 0 = disable, 1 = enable 1 usb host [6] control hclk into usb host block. 0 = disable, 1 = enable 1 lcdc [5] control hclk into lcdc block. 0 = disable, 1 = enable 1 nand flash controller [4] control hclk into nand flash controller block. 0 = disable, 1 = enable 1 sleep [3] control sleep mode of S3C2440X. 0 = disable, 1 = transition to sleep mode 0 idle bit [2] enter idle mode. this bit is not cleared automatically. 0 = disable, 1 = transition to idle mode 0 reserved [1] reserved 0 reserved [0] reserved 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. clock & power management S3C2440X 7 - 24 clock slow control (clkslow) register register address r/w description reset value clkslow 0x4c000010 r/w slow clock control register 0x00000004 clkslow bit description initial state uclk_on [7] 0: uclk on (upll is also turned on and the upll lock time is inserted automatically.) 1: uclk off (upll is also turned off.) 0 reserved [6] reserved ? mpll_off [5] 0: turn on pll. after pll stabilization time (minimum 300us), slow_bit canbeclearedto0. 1: turn off pll. pll is turned off only when slow_bit is 1. 0 slow_bit [4] 0 : fclk = mpll (mpll output) 1: slow mode fclk = input clock/(2xslow_val), when slow_val>0 fclk = input clock, when slow_val=0. input clock = xtipll or extclk 0 reserved [3] ? ? slow_val [2:0] the divider value for the slow clock when slow_bit is on. 0x4
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X clock & power management 7 - 25 clock divider control (clkdivn) register register address r/w description reset value clkdivn 0x4c000014 r/w clock divider control register 0x00000000 clkdivn bit description initial state divn_upll [3] uclk select register(uclk must be 48mhz for usb) 0: uclk = upll clock 1: uclk = upll clock / 2 set to 0, when upll clock is set as 48mhz set to 1. when upll clock is set as 96mhz. 0 hdivn [2:1] 00: hclk has the clock same as the fclk/1. 01: hclk has the clock same as the fclk/2. 10: hclk has the clock same as the fclk/4. 11: hclk has the clock same as the fclk/3. 0 pdivn [0] 0: pclk has the clock same as the hclk/1. 1: pclk has the clock same as the hclk/2. 0 camera clock divider (camdivn) register register address r/w description reset value camdivn 0x4c000018 r/w camera clock divider register 0x00000000 camdivn bit description initial state camclk_sel [4] 0:use camclk with upll output(camclk=upll output). 1:camclk is divided by camclk_div value. 0 camclk_div [3:0] camclk divide factor setting register(0 ? 15). camera clock = upll / [(camclk_div +1)x2]. this bit is valid when camclk_sel=1. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor dma 8-1 8 dma overview the S3C2440X supports four-channel dma controller that is located between the system bus and the peripheral bus. each channel of dma controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. in other words, each channel can handle the following four cases: 1) both source and destination are in the system bus, 2) the source is in the system bus while the destination is in the peripheral bus, 3) the source is in the peripheral bus while the destination is in the system bus, and 4) both source and destination are in the peripheral bus. the main advantage of the dma is that it can transfer the data without cpu intervention. the operation of dma can be initiated by software, or requests from internal peripherals or external request pins.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. dma S3C2440X risc microprocessor 8-2 dma request sources each channel of the dma controller can select one of dma request source among four dma sources if h/w dma request mode is selected by dcon register. (note that if s/w request mode is selected, this dma request sources have no meaning at all.) table 8-1 shows four dma sources for each channel. source0 source1 source2 source3 source4 ch-0 nxdreq0 uart0 sdi timer usb device ep1 ch-1 nxdreq1 uart1 i2ssdi spi0 usb device ep2 ch-2 i2ssdo i2ssdi sdi timer usb device ep3 ch-3 uart2 sdi spi1 timer usb device ep4 table 8-1. dma request sources for each channel here, nxdreq0 and nxdreq1 represent two external sources(external devices), and i2ssdo and i2ssdi represent iis transmitting and receiving, respectively. dma operation dma uses three-state fsm ( f inite s tate m achine) for its operation, which is described in the three following steps: state-1. as an initial state, the dma waits for a dma request. if it comes, it goes to state-2. at this state, dma ack and int req are 0. state-2. in this state, dma ack becomes 1 and the counter (curr_tc) is loaded from dcon[19:0] register. note that the dma ack remains 1 until it is cleared later. state-3. in this state, sub-fsm handling the atomic operation of dma is initiated. the sub-fsm reads the data from the source address and then writes it to destination address. in this operation, data size and transfer size (single or burst) are considered. this operation is repeated until the counter (curr_tc) becomes 0 in whole service mode, while performed only once in single service mode. the main fsm (this fsm) counts down the curr_tc when the sub-fsm finishes each of atomic operation. in addition, this main fsm asserts the int req signal when curr_tc becomes 0 and the interrupt setting of dcon[29] register is set to 1. in addition, it clears dma ack if one of the following conditions is met. 1) curr_tc becomes 0 in the whole service mode 2) atomic operation finishes in the single service mode. note that in the single service mode, these three states of main fsm are performed and then stops, and waits for another dma req. and if dma req comes in, all three states are repeated. therefore, dma ack is asserted and then deasserted for each atomic transfer. in contrast, in the whole service mode, main fsm waits at state-3 until curr_tc becomes 0. therefore, dma ack is asserted during all the transfers and then deasserted when tc reaches 0. however, int req is asserted only if curr_tc becomes 0 regardless of the service mode (single service mode or whole service mode).
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor dma 8-3 external dma dreq/dack protocol there are three types of external dma request/acknowledge protocols (single service demand, single service handshake and whole service handshake mode). each type defines how the signals like dma request and acknowledge are related to these protocols. basic dma timing the dma service means performing paired reads and writes cycles during dma operation, which can make one dma operation. figure 8-1 shows the basic timing in the dma operation of the S3C2440X. - the setup time and the delay time of xnxdreq and xnxdack are the same in all the modes. - if the completion of xnxdreq meets its setup time, it is synchronized twice and then xnxdack is asserted. - after assertion of xnxdack, dma requests the bus and if it gets the bus it performs its operations. xnxdack is deasserted when dma operation is completed. xsclk 9.3ns setup 9.3ns setup 6.8ns delay 6.6ns delay read write min. 2xsclk xnxdreq xnxdack min. 3xsclk figure 8-1. basic dma timing diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. dma S3C2440X risc microprocessor 8-4 demand/handshake mode comparison demand and handshake modes are related to the protocol between xnxdreq and xnxdack. figure 8-2 shows the differences between the two modes. at the end of one transfer (single/burst transfer), dma checks the state of double-synched xnxdreq. demand mode - if xnxdreq remains asserted, the next transfer starts immediately. otherwise it waits for xnxdreq to be asserted. handshake mode - if xnxdreq is deasserted, dma deasserts xnxdack in 2cycles. otherwise it waits until xnxdreq is deasserted. caution: xnxdreq has to be asserted (low) only after the deassertion (high) of xnxdack. demand mode xsclk xnxdack xnxdack xnxdreq xnxdreq 2cycles double synch read write read write handshake mode bus acquisiton actual transfer 1st transfer 2nd transfer 2cycles read write double synch 2cycles figure 8-2. demand/handshake mode comparison
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor dma 8-5 transfer size - there are two different transfer sizes; unit and burst 4. - dma holds the bus firmly during the transfer of the chunk of data. thus, other bus masters cannot get the bus. burst 4 transfer size there will be four sequential reads and writes respectively are performed in the burst 4 transfer. * note : unit transfer size: one read and one write are performed. xsclk xnxdreq xnxdack read read read write write write read write 3cycles double synch figure 8-3. burst 4 transfer size
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. dma S3C2440X risc microprocessor 8-6 examples single service in demand mode with unit transfer size theassertionofxnxdreq will be a need for every unit transfer (single service mode). the operation continues while the xnxdreq is asserted (demand mode), and one pair of read and write (single transfer size) is performed. xsclk xnxdreq xnxdack xsclk xnxdreq xnxdack read write read write double synch figure 8-4. single service in demand mode with unit transfer size single service in handshake mode with unit transfer size xnxdreq xnxdack xsclk read write read write 2cycles double synch figure 8-5. single service in handshake mode with unit transfer size whole service in handshake mode with unit transfer size xsclk xnxdreq xnxdack read write read write read write 2cycles 2cycles 3cycles double synch figure 8-6. whole service in handshake mode with unit transfer size
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor dma 8-7 dma special registers each dma channel has nine control registers (36 in total since there are four channels for dma controller). six of the control registers control the dma transfer, and other three ones monitor the status of dma controller. the details of those registers are as follows. dma initial source (disrc) register register address r/w description reset value disrc0 0x4b000000 r/w dma 0 initial source register 0x00000000 disrc1 0x4b000040 r/w dma 1 initial source register 0x00000000 disrc2 0x4b000080 r/w dma 2 initial source register 0x00000000 disrc3 0x4b0000c0 r/w dma 3 initial source register 0x00000000 disrcn bit description initial state s_addr [30:0] base address (start address) of source data to transfer. this bit value will be loaded into curr_src only if the curr_src is 0 and the dma ack is 1. 0x00000000 dma initial source control (disrcc) register register address r/w description reset value disrcc0 0x4b000004 r/w dma 0 initial source control register 0x00000000 disrcc1 0x4b000044 r/w dma 1 initial source control register 0x00000000 disrcc2 0x4b000084 r/w dma 2 initial source control register 0x00000000 disrcc3 0x4b0000c4 r/w dma 3 initial source control register 0x00000000 disrccn bit description initial state loc [1] bit 1 is used to select the location of source. 0: the source is in the system bus (ahb). 1: the source is in the peripheral bus (apb). 0 inc [0] bit 0 is used to select the address increment. 0 = increment 1= fixed if it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. if it is 1, the address is not changed after the transfer. (in the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer.) 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. dma S3C2440X risc microprocessor 8-8 dma initial destination (didst) register register address r/w description reset value didst0 0x4b000008 r/w dma 0 initial destination register 0x00000000 didst1 0x4b000048 r/w dma 1 initial destination register 0x00000000 didst2 0x4b000088 r/w dma 2 initial destination register 0x00000000 didst3 0x4b0000b8 r/w dma 3 initial destination register 0x00000000 didstn bit description initial state d_addr [30:0] base address (start address) of destination for the transfer. this bit value will be loaded into curr_src only if the curr_dst is 0 and the dma ack is 1. 0x00000000 dma initial destination control (didstc) register register address r/w description reset value didstc0 0x4b00000c r/w dma 0 initial destination control register 0x00000000 didstc1 0x4b00004c r/w dma 1 initial destination control register 0x00000000 didstc2 0x4b00008c r/w dma 2 initial destination control register 0x00000000 didstc3 0x4b0000cc r/w dma 3 initial destination control register 0x00000000 didstcn bit description initial state chk_int [2] select interrupt occurrence time when auto reload is setting. 0 : interrupt will occur when tc reaches 0. 1 : interrupt will occur after autoreload is performed. 0 loc [1] bit 1 is used to select the location of destination. 0: the destination is in the system bus (ahb). 1: the destination is in the peripheral bus (apb). 0 inc [0] bit 0 is used to select the address increment. 0 = increment 1= fixed if it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. if it is 1, the address is not changed after the transfer. (in the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer.) 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor dma 8-9 dma control (dcon) register register address r/w description reset value dcon0 0x4b000010 r/w dma 0 control register 0x00000000 dcon1 0x4b000050 r/w dma 1 control register 0x00000000 dcon2 0x4b000090 r/w dma 2 control register 0x00000000 dcon3 0x4b0000d0 r/w dma 3 control register 0x00000000 dconn bit description initial state dmd_hs [31] select one between demand mode and handshake mode. 0: demand mode will be selected. 1: handshake mode will be selected. in both modes, dma controller starts its transfer and asserts dack for a given asserted dreq. the difference between the two modes is whether it waits for the deasserted dack or not. in the handshake mode, dma controller waits for the deasserted dreq before starting a new transfer. if it finds the deasserted dreq, it deasserts dack and waits for another asserted dreq. in contrast, in the demand mode, dma controller does not wait until the dreq is deasserted. it just deasserts dack and then starts another transfer if dreq is asserted. we recommend using handshake mode for external dma request sources to prevent unintended starts of new transfers. 0 sync [30] select dreq/dack synchronization. 0: dreq and dack are synchronized to pclk (apb clock). 1: dreq and dack are synchronized to hclk (ahb clock). therefore, for devices attached to ahb system bus, this bit has to be set to 1, while for those attached to apb system, it should be set to 0. for the devices attached to external systems, the user should select this bit depending on which the external system is synchronized with between ahb system and apb system. 0 int [29] enable/disable the interrupt setting for curr_tc (terminal count) 0: curr_tc interrupt is disabled. the user has to view the transfer count in the status register (i.e. polling). 1: interrupt request is generated when all the transfer is done (i.e. curr_tc becomes 0). 0 tsz [28] select the transfer size of an atomic transfer (i.e. transfer performed each time dma owns the bus before releasing the bus). 0: a unit transfer is performed. 1: a burst transfer of length four is performed. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. dma S3C2440X risc microprocessor 8-10 dconn bit description initial state servmode [27] select the service mode between single service mode and whole service mode. 0: single service mode is selected in which after each atomic transfer (single or burst of length four) dma stops and waits for another dma request. 1: whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0. in this mode, additional request are not required. note that even in the whole service mode, dma releases the bus after each atomic transfer and then tries to re-get the bus to prevent starving of other bus masters. 0 hwsrcsel [26:24] select dma request source for each dma. dcon0: 000:nxdreq0 001:uart0 010:sdi 011:timer 100:usb device ep1 dcon1: 000:nxdreq1 001:uart1 010:i2ssdi 011:spi 100:usb device ep2 dcon2: 000:i2ssdo 001:i2ssdi 010:sdi 011:timer 100:usb device ep3 dcon3: 000:uart2 001:sdi 010:spi 011:timer 100:usb device ep4 these bits control the 4-1 mux to select the dma request source of each dma. these bits have meanings only if h/w request mode is selected by dconn[23]. 00 swhw_sel [23] select the dma source between software (s/w request mode) and hardware (h/w request mode). 0: s/w request mode is selected and dma is triggered by setting sw_trig bit of dmasktrig control register. 1: dma source selected by bit[26:24] triggers the dma operation. 0 reload [22] set the reload on/off option. 0: auto reload is performed when a current value of transfer count becomes 0 (i.e. all the required transfers are performed). 1: dma channel (dma req) is turned off when a current value of transfer count becomes 0. the channel on/off bit (dmasktrign[1]) is set to 0 (dreq off) to prevent unintended further start of new dma operation. 0 dsz [21:20] data size to be transferred. 00 = byte 01 = half word 10 = word 11 = reserved 00 tc [19:0] initial transfer count (or transfer beat). note that the actual number of bytes that are transferred is computed by the following equation: dsz x tsz x tc. where, dsz, tsz (1 or 4), and tc represent data size (dconn[21:20]), transfer size (dconn[28]), and initial transfer count, respectively. this value will be loaded into curr_tc only if the curr_tc is 0 and the dma ack is 1. 00000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor dma 8-11 dma status (dstat) register register address r/w description reset value dstat0 0x4b000014 r dma 0 count register 000000h dstat1 0x4b000054 r dma 1 count register 000000h dstat2 0x4b000094 r dma 2 count register 000000h dstat3 0x4b0000d4 r dma 3 count register 000000h dstatn bit description initial state stat [21:20] status of this dma controller. 00: indicates that dma controller is ready for another dma request. 01: indicates that dma controller is busy for transfers. 00b curr_tc [19:0] current value of transfer count. note that transfer count is initially set to the value of dconn[19:0] register and decreased by one at the end of every atomic transfer. 00000h
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. dma S3C2440X risc microprocessor 8-12 dma current source (dcsrc) register register address r/w description reset value dcsrc0 0x4b000018 r dma 0 current source register 0x00000000 dcsrc1 0x4b000058 r dma 1 current source register 0x00000000 dcsrc2 0x4b000098 r dma 2 current source register 0x00000000 dcsrc3 0x4b0000d8 r dma 3 current source register 0x00000000 dcsrcn bit description initial state curr_src [30:0] current source address for dman 0x00000000 current destination (dcdst) register register address r/w description reset value dcdst0 0x4b00001c r dma 0 current destination register 0x00000000 dcdst1 0x4b00005c r dma 1 current destination register 0x00000000 dcdst2 0x4b00009c r dma 2 current destination register 0x00000000 dcdst3 0x4b0000dc r dma 3 current destination register 0x00000000 dcdstn bit description initial state curr_dst [30:0] current destination address for dman 0x00000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor dma 8-13 dma mask trigger (dmasktrig) register register address r/w description reset value dmasktrig0 0x4b000020 r/w dma 0 mask trigger register 000 dmasktrig1 0x4b000060 r/w dma 1 mask trigger register 000 dmasktrig2 0x4b0000a0 r/w dma 2 mask trigger register 000 dmasktrig3 0x4b0000e0 r/w dma 3 mask trigger register 000 dmasktrign bit description initial state stop [2] stop the dma operation. 1: dma stops as soon as the current atomic transfer ends. if there is no current running atomic transfer, dma stops immediately. the curr_tc, curr_src, and curr_dst will be 0. note: due to possible current atomic transfer, ?stop? operation may take several cycles. the finish of the operation (i.e. actual stop time) can be detected as soon as the channel on/off bit (dmasktrign[1]) is set to off. this stop is ?actual stop?. 0 on_off [1] dma channel on/off bit. 0: dma channel is turned off. (dma request to this channel is ignored.) 1: dma channel is turned on and the dma request is handled. this bit is automatically set to off if we set the dconn[22] bit to ?no auto reload? and/or stop bit of dmasktrign to ?stop?. note that when dcon[22] bit is "no auto reload", this bit becomes 0 when curr_tc reaches 0. if the stop bit is 1, this bit becomes 0 as soon as the current atomic transfer is completed. note. this bit should not be changed manually during dma operations (i.e. this has to be changed only by using dcon[22] or stop bit). 0 sw_trig [0] trigger the dma channel in s/w request mode. 1: it requests a dma operation to this controller. note that this trigger gets effective after s/w request mode has to be selected (dconn[23]) and channel on_off bit has to be set to 1 (channel on). when dma operation starts, this bit is cleared automatically. 0 note :you are allowed to change the values of disrc register, didst registers, and tc field of dcon register. those changes take effect only after the finish of current transfer (i.e. when curr_tc becomes 0). on the other hand, any change made to other registers and/or fields takes immediate effect. therefore, be careful in changing those registers and fields.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. dma S3C2440X risc microprocessor 8-14 notes
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-1 i/o ports overview S3C2440X has 130 multi-functional input/output port pins. there are eight ports: - port a(gpa): 25-output port - port b(gpb): 11-input/out port - port c(gpc): 16-input/output port - port d(gpd): 16-input/output port - port e(gpe): 16-input/output port - port f(gpf): 8-input/output port - port g(gpg): 16-input/output port - port h(gph): 9-input/output port - port j(gpj): 13-input/output port each port can be easily configured by software to meet various system configurations and design requirements. you have to define which function of each pin is used before starting the main program. if a pin is not used for multiplexed functions, the pin can be configured as i/o ports. initial pin states are configured seamlessly to avoid problems.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-2 table 9-1. S3C2440X port configuration(sheet 1 of 5) port a selectable pin functions gpa22 output only nfce ?? gpa21 output only nrstout ?? gpa20 output only nfre ?? gpa19 output only nfwe ?? gpa18 output only ale ?? gpa17 output only cle ?? gpa16 output only ngcs5 ?? gpa15 output only ngcs4 ?? gpa14 output only ngcs3 ?? gpa13 output only ngcs2 ?? gpa12 output only ngcs1 ?? gpa11 output only addr26 ?? gpa10 output only addr25 ?? gpa9 output only addr24 ?? gpa8 output only addr23 ?? gpa7 output only addr22 ?? gpa6 output only addr21 ?? gpa5 output only addr20 ?? gpa4 output only addr19 ?? gpa3 output only addr18 ?? gpa2 output only addr17 ?? gpa1 output only addr16 ?? gpa0 output only addr0 ??
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-3 table 9-1. S3C2440X port configuration(sheet 2 of 5) port b selectable pin functions gpb10 input/output nxdreq0 ?? gpb9 input/output nxdack0 ?? gpb8 input/output nxdreq1 ?? gpb7 input/output nxdack1 ?? gpb6 input/output nxbreq ?? gpb5 input/output nxback ?? gpb4 input/output tclk0 ?? gpb3 input/output tout3 ?? gpb2 input/output tout2 ?? gpb1 input/output tout1 ?? gpb0 input/output tout0 ?? port c selectable pin functions gpc15 input/output vd7 ?? gpc14 input/output vd6 ?? gpc13 input/output vd5 ?? gpc12 input/output vd4 ?? gpc11 input/output vd3 ?? gpc10 input/output vd2 ?? gpc9 input/output vd1 ?? gpc8 input/output vd0 ?? gpc7 input/output lcd_lpcrevb ?? gpc6 input/output lcd_lpcrev ?? gpc5 input/output lcd_lpcoe ?? gpc4 input/output vm ?? gpc3 input/output vframe ?? gpc2 input/output vline ?? gpc1 input/output vclk ?? gpc0 input/output lend ??
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-4 table 9-1. S3C2440X port configuration(sheet 3 of 5) port d selectable pin functions gpd15 input/output vd23 nss0 ? gpd14 input/output vd22 nss1 ? gpd13 input/output vd21 ?? gpd12 input/output vd20 ?? gpd11 input/output vd19 ?? gpd10 input/output vd18 spiclk1 ? gpd9 input/output vd17 spimosi1 ? gpd8 input/output vd16 spimiso1 ? gpd7 input/output vd15 ?? gpd6 input/output vd14 ?? gpd5 input/output vd13 ?? gpd4 input/output vd12 ?? gpd3 input/output vd11 ?? gpd2 input/output vd10 ?? gpd1 input/output vd9 ?? gpd0 input/output vd8 ?? port e selectable pin functions gpe15 input/output iicsda ?? gpe14 input/output iicscl ?? gpe13 input/output spiclk0 ?? gpe12 input/output spimosi0 ?? gpe11 input/output spimiso0 ?? gpe10 input/output sddat3 ?? gpe9 input/output sddat2 ?? gpe8 input/output sddat1 ?? gpe7 input/output sddat0 ?? gpe6 input/output sdcmd ?? gpe5 input/output sdclk ?? gpe4 input/output i2ssdo i2ssdi ? gpe3 input/output i2ssdi nss0 ? gpe2 input/output cdclk ?? gpe1 input/output i2ssclk ?? gpe0 input/output i2slrck ??
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-5 table 9-1. S3C2440X port configuration(sheet 4 of 5) port f selectable pin functions gpf7 input/output eint7 ?? gpf6 input/output eint6 ?? gpf5 input/output eint5 ?? gpf4 input/output eint4 ?? gpf3 input/output eint3 ?? gpf2 input/output eint2 gpf1 input/output eint1 gpf0 input/output eint0 port g selectable pin functions gpg15 input/output eint23 ?? gpg14 input/output eint22 ?? gpg13 input/output eint21 ?? gpg12 input/output eint20 ?? gpg11 input/output eint19 tclk1 ? gpg10 input/output eint18 ncts1 ? gpg9 input/output eint17 nrts1 ? gpg8 input/output eint16 ?? gpg7 input/output eint15 spiclk1 ? gpg6 input/output eint14 spimosi1 ? gpg5 input/output eint13 spimiso1 ? gpg4 input/output eint12 lcd_pwren ? gpg3 input/output eint11 nss1 ? gpg2 input/output eint10 nss0 ? gpg1 input/output eint9 ?? gpg0 input/output eint8 ??
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-6 table 9-1. S3C2440X port configuration(sheet 5 of 5) port h selectable pin functions gph10 input/output clkout1 ?? gph9 input/output clkout0 ?? gph8 input/output uclk ?? gph7 input/output rxd2 ncts1 ? gph6 input/output txd2 nrts1 ? gph5 input/output rxd1 ?? gph4 input/output txd1 ?? gph3 input/output rxd0 ?? gph2 input/output txd0 ?? gph1 input/output nrts0 ?? gph0 input/output ncts0 ?? port j selectable pin functions gpj12 input/output camreset ?? gpj11 input/output camclkout ?? gpj10 input/output camhref ?? gpj9 input/output camvsync ?? gpj8 input/output cmapclkin ?? gpj7 input/output camdata7 ?? gpj6 input/output camdata6 ?? gpj5 input/output camdata5 ?? gpj4 input/output camdata4 ?? gpj3 input/output camdata3 ?? gpj2 input/output camdata2 ?? gpj1 input/output camdata1 ?? gpj0 input/output camdata0 ??
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-7 port control descriptions port configuration register(gpacon-gpjcon) in S3C2440X, most pins are multiplexed pins. so, it is determined which function is selected for each pins. the pncon(port control register) determines which function is used for each pin. if pe0 ? pe7 is used for the wakeup signal in power down mode, these ports must be configured in interrupt mode. port data register(gpadat-gpjdat) if ports are configured as output ports, data can be written to the corresponding bit of pndat. if ports are configured as input ports, the data can be read from the corresponding bit of pndat. port pull-up register(gpbup-gpjup) the port pull-up register controls the pull-up resister enable/disable of each port group. when the corresponding bit is 0, the pull-up resister of the pin is enabled. when 1, the pull-up resister is disabled. if the port pull-up register is enabled then the pull-up resisters work without pin?s functional setting(input, output, datan, eintn and etc) miscellaneous control register this register controls data port pull-up resister in sleep mode, usb pad, and clkout selection. external interrupt control register the 24 external interrupts are requested by various signaling methods. the extint register configures the signaling method among the low level trigger, high level trigger, falling edge trigger, rising edge trigger, and both edge trigger for the external interrupt request because each external interrupt pin has a digital filter, the interrupt controller can recognize the request signal that is longer than 3 clocks. eint[15:0] are used for wakeup sources.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-8 i/o port control register port a control registers(gpacon, gpadat) register address r/w description reset value gpacon 0x56000000 r/w configures the pins of port a 0xffffff gpadat 0x56000004 r/w the data register for port a undef. reserved 0x56000008 - reserved undef reserved 0x5600000c - reserved undef gpacon bit description gpa24 [24] reserved gpa23 [23] reserved gpa22 [22] 0 = output 1 = nfce gpa21 [21] 0 = output 1 = nrstout gpa20 [20] 0 = output 1 = nfre gpa19 [19] 0 = output 1 = nfwe gpa18 [18] 0 = output 1 = ale gpa17 [17] 0 = output 1 = cle gpa16 [16] 0 = output 1 = ngcs[5] gpa15 [15] 0 = output 1 = ngcs[4] gpa14 [14] 0 = output 1 = ngcs[3] gpa13 [13] 0 = output 1 = ngcs[2] gpa12 [12] 0 = output 1 = ngcs[1] gpa11 [11] 0 = output 1 = addr26 gpa10 [10] 0 = output 1 = addr25 gpa9 [9] 0 = output 1 = addr24 gpa8 [8] 0 = output 1 = addr23 gpa7 [7] 0 = output 1 = addr22 gpa6 [6] 0 = output 1 = addr21 gpa5 [5] 0 = output 1 = addr20 gpa4 [4] 0 = output 1 = addr19 gpa3 [3] 0 = output 1 = addr18 gpa2 [2] 0 = output 1 = addr17 gpa1 [1] 0 = output 1 = addr16 gpa0 [0] 0 = output 1 = addr0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-9 gpadat bit description gpa[24:0] [24:0] when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. nrstout = nreset & nwdtrst & sw_reset
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-10 port b control registers(gpbcon, gpbdat, gpbup) register address r/w description reset value gpbcon 0x56000010 r/w configures the pins of port b 0x0 gpbdat 0x56000014 r/w the data register for port b undef. gpbup 0x56000018 r/w pull-up disable register for port b 0x0 reserved 0x5600001c pbcon bit description gpb10 [21:20] 00 = input 01 = output 10 = nxdreq0 11 = reserved gpb9 [19:18] 00 = input 01 = output 10 = nxdack0 11 = reserved gpb8 [17:16] 00 = input 01 = output 10 = nxdreq1 11 = reserved gpb7 [15:14] 00 = input 01 = output 10 = nxdack1 11 = reserved gpb6 [13:12] 00 = input 01 = output 10 = nxbreq 11 = reserved gpb5 [11:10] 00 = input 01 = output 10 = nxback 11 = reserved gpb4 [9:8] 00 = input 01 = output 10 = tclk [0] 11 = reserved gpb3 [7:6] 00 = input 01 = output 10 = tout3 11 = reserved gpb2 [5:4] 00 = input 01 = output 10 = tout2 11 = reserved] gpb1 [3:2] 00 = input 01 = output 10 = tout1 11 = reserved gpb0 [1:0] 00 = input 01 = output 10 = tout0 11 = reserved gpbdat bit description gpb[10:0] [10:0] when the port is configured as input port, the corresponding bit is the pin state. when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. gpbup bit description gpb[10:0] [10:0] 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-11 port c control registers(gpccon, gpcdat, gpcup) register address r/w description reset value gpccon 0x56000020 r/w configures the pins of port c 0x0 gpcdat 0x56000024 r/w the data register for port c undef. gpcup 0x56000028 r/w pull-up disable register for port c 0x0 reserved 0x5600002c - - - gpccon bit description gpc15 [31:30] 00 = input 01 = output 10 = vd[7] 11 = reserved gpc14 [29:28] 00 = input 01 = output 10 = vd[6] 11 = reserved gpc13 [27:26] 00 = input 01 = output 10 = vd[5] 11 = reserved gpc12 [25:24] 00 = input 01 = output 10 = vd[4] 11 = reserved gpc11 [23:22] 00 = input 01 = output 10 = vd[3] 11 = reserved gpc10 [21:20] 00 = input 01 = output 10 = vd[2] 11 = reserved gpc9 [19:18] 00 = input 01 = output 10 = vd[1] 11 = reserved gpc8 [17:16] 00 = input 01 = output 10 = vd[0] 11 = reserved gpc7 [15:14] 00 = input 01 = output 10 = lcd_lpcrevb 11 = reserved gpc6 [13:12] 00 = input 01 = output 10 = lcd_lpcrev 11 = reserved gpc5 [11:10] 00 = input 01 = output 10 = lcd_lpcoe 11 = reserved gpc4 [9:8] 00 = input 01 = output 10 = vm 11 = i2ssdi gpc3 [7:6] 00 = input 01 = output 10 = vframe 11 = reserved gpc2 [5:4] 00 = input 01 = output 10 = vline 11 = reserved gpc1 [3:2] 00 = input 01 = output 10 = vclk 11 = reserved gpc0 [1:0] 00 = input 01 = output 10 = lend 11 = reserved
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-12 gpcdat bit description gpc[15:0] [15:0] when the port is configured as input port, the corresponding bit is the pin state. when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. gpcup bit description gpc[15:0] [15:0] 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-13 port d control registers(gpdcon, gpddat, gpdup) register address r/w description reset value gpdcon 0x56000030 r/w configures the pins of port d 0x0 gpddat 0x56000034 r/w the data register for port d undef. gpdup 0x56000038 r/w pull-up disable register for port d 0xf000 reserved 0x5600003c - gpdcon bit description gpd15 [31:30] 00 = input 01 = output 10 = vd[23] 11 = nss0 gpd14 [29:28] 00 = input 01 = output 10 = vd[22] 11 = nss1 gpd13 [27:26] 00 = input 01 = output 10 = vd[21] 11 = reserved gpd12 [25:24] 00 = input 01 = output 10 = vd[20] 11 = reserved gpd11 [23:22] 00 = input 01 = output 10 = vd[19] 11 = reserved gpd10 [21:20] 00 = input 01 = output 10 = vd[18] 11 = spiclk1 gpd9 [19:18] 00 = input 01 = output 10 = vd[17] 11 = spimosi1 gpd8 [17:16] 00 = input 01 = output 10 = vd[16] 11 = spimiso1 gpd7 [15:14] 00 = input 01 = output 10 = vd[15] 11 = reserved gpd6 [13:12] 00 = input 01 = output 10 = vd[14] 11 = reserved gpd5 [11:10] 00 = input 01 = output 10 = vd[13] 11 = reserved gpd4 [9:8] 00 = input 01 = output 10 = vd[12] 11 = reserved gpd3 [7:6] 00 = input 01 = output 10 = vd[11] 11 = reserved gpd2 [5:4] 00 = input 01 = output 10 = vd[10] 11 = reserved gpd1 [3:2] 00 = input 01 = output 10 = vd[9] 11 = reserved gpd0 [1:0] 00 = input 01 = output 10 = vd[8] 11 = reserved
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-14 gpddat bit description gpd[15:0] [15:0] when the port is configured as input port, the corresponding bit is the pin state. when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. gpdup bit description gpd[15:0] [15:0] 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-15 port e control registers(gpecon, gpedat, gpeup) register address r/w description reset value gpecon 0x56000040 r/w configures the pins of port e 0x0 gpedat 0x56000044 r/w the data register for port e undef. gpeup 0x56000048 r/w pull-up disable register for port e 0x0000 reserved 0x5600004c - - - gpecon bit description gpe15 [31:30] 00 = input 01 = output 10 = iicsda 11 = reserved this pad is open-drain, there is no pull-up option. gpe14 [29:28] 00 = input 01 = output 10 = iicscl 11 = reserved this pad is open-drain, there is no pull-up option. gpe13 [27:26] 00 = input 01 = output 10 = spiclk0 11 = reserved gpe12 [25:24] 00 = input 01 = output 10 = spimosi0 11 = reserved gpe11 [23:22] 00 = input 01 = output 10 = spimiso0 11 = reserved gpe10 [21:20] 00 = input 01 = output 10 = sddat3 11 = reserved gpe9 [19:18] 00 = input 01 = output 10 = sddat2 11 = reserved gpe8 [17:16] 00 = input 01 = output 10 = sddat1 11 = reserved gpe7 [15:14] 00 = input 01 = output 10 = sddat0 11 = reserved gpe6 [13:12] 00 = input 01 = output 10 = sdcmd 11 = reserved gpe5 [11:10] 00 = input 01 = output 10 = sdclk 11 = reserved gpe4 [9:8] 00 = input 01 = output 10 = i2sdo 11 = i2ssdi gpe3 [7:6] 00 = input 01 = output 10 = i2sdi 11 = nss0 gpe2 [5:4] 00 = input 01 = output 10 = cdclk 11 = reserved gpe1 [3:2] 00 = input 01 = output 10 = i2ssclk 11 = reserved gpe0 [1:0] 00 = input 01 = output 10 = i2slrck 11 = reserved
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-16 . gpedat bit description gpe[15:0] [15:0] when the port is configured as an input port, the corresponding bit is the pin state. when the port is configured as an output port, the pin state is the same as the corresponding bit. when the port is configured as a functional pin, the undefined value will be read. gpeup bit description gpe[13:0] [13:0] 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-17 port f control registers(gpfcon, gpfdat) if gpf0 - gpf7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. register address r/w description reset value gpfcon 0x56000050 r/w configures the pins of port f 0x0 gpfdat 0x56000054 r/w the data register for port f undef. gpfup 0x56000058 r/w pull-up disable register for port f 0x000 reserved 0x5600005c - - gpfcon bit description gpf7 [15:14] 00 = input 01 = output 10 = eint[7] 11 = reserved gpf6 [13:12] 00 = input 01 = output 10 = eint[6] 11 = reserved gpf5 [11:10] 00 = input 01 = output 10 = eint[5] 11 = reserved gpf4 [9:8] 00 = input 01 = output 10 = eint[4] 11 = reserved gpf3 [7:6] 00 = input 01 = output 10 = eint[3] 11 = reserved gpf2 [5:4] 00 = input 01 = output 10 = eint2] 11 = reserved gpf1 [3:2] 00 = input 01 = output 10 = eint[1] 11 = reserved gpf0 [1:0] 00 = input 01 = output 10 = eint[0] 11 = reserved gpfdat bit description gpf[7:0] [7:0] when the port is configured as an input port, the corresponding bit is the pin state. when the port is configured as an output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. gpfup bit description gpf[7:0] [7:0] 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-18 port g control registers(gpgcon, gpgdat) if gpg0 - gpgf7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. register address r/w description reset value gpgcon 0x56000060 r/w configures the pins of port g 0x0 gpgdat 0x56000064 r/w the data register for port g undef. gpgup 0x56000068 r/w pull-up disable register for port g 0xfc00 reserved 0x5600006c - - - gpgcon bit description gpg15* [31:30] 00 = input 01 = output 10 = eint[23] 11 = reserved gpg14* [29:28] 00 = input 01 = output 10 = eint[22] 11 = reserved gpg13* [27:26] 00 = input 01 = output 10 = eint[21] 11 = reserved gpg12 [25:24] 00 = input 01 = output 10 = eint[20] 11 = reserved gpg11 [23:22] 00 = input 01 = output 10 = eint[19] 11 = tclk[1] gpg10 [21:20] 00 = input 01 = output 10 = eint[18] 11 = ncts1 gpg9 [19:18] 00 = input 01 = output 10 = eint[17] 11 = nrts1 gpg8 [17:16] 00 = input 01 = output 10 = eint[16] 11 = reserved gpg7 [15:14] 00 = input 01 = output 10 = eint[15] 11 = spiclk1 gpg6 [13:12] 00 = input 01 = output 10 = eint[14] 11 = spimosi1 gpg5 [11:10] 00 = input 01 = output 10 = eint[13] 11 = spimiso1 gpg4 [9:8] 00 = input 01 = output 10 = eint[12] 11 = lcd_pwrdn gpg3 [7:6] 00 = input 01 = output 10 = eint[11] 11 = nss1 gpg2 [5:4] 00 = input 01 = output 10 = eint[10] 11 = nss0 gpg1 [3:2] 00 = input 01 = output 10 = eint[9] 11 = reserved gpg0 [1:0] 00 = input 01 = output 10 = eint[8] 11 = reserved note: gpg[15:13] must be selected as input in nand-booting mode.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-19 gpgdat bit description gpg[15:0] [15:0] when the port is configured as an input port, the corresponding bit is the pin state. when the port is configured as an output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. gpgup bit description gpg[15:0] [15:0] 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-20 port h control registers(gphcon, gphdat) if gpf0 - gpf7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. register address r/w description reset value gphcon 0x56000070 r/w configures the pins of port h 0x0 gphdat 0x56000074 r/w the data register for port h undef. gphup 0x56000078 r/w pull-up disable register for port h 0x000 reserved 0x5600007c - - gphcon bit description gph10 [21:20] 00 = input 01 = output 10 = clkout1 11 = reserved gph9 [19:18] 00 = input 01 = output 10 = clkout0 11 = reserved gph8 [17:16] 00 = input 01 = output 10 = uartclk 11 = reserved gph7 [15:14] 00 = input 01 = output 10 = rxd[2] 11 = ncts1 gph6 [13:12] 00 = input 01 = output 10 = txd[2] 11 = nrts1 gph5 [11:10] 00 = input 01 = output 10 = rxd[1] 11 = reserved gph4 [9:8] 00 = input 01 = output 10 = txd[1] 11 = reserved gph3 [7:6] 00 = input 01 = output 10 = rxd[0] 11 = reserved gph2 [5:4] 00 = input 01 = output 10 = txd[0] 11 = reserved gph1 [3:2] 00 = input 01 = output 10 = nrts0 11 = reserved gph0 [1:0] 00 = input 01 = output 10 = ncts0 11 = reserved
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-21 gphdat bit description gph[10:0] [10:0] when the port is configured as an input port, the corresponding bit is the pin state. when the port is configured as an output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. gphup bit description gph[10:0] [10:0] 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-22 port j control registers(gpjcon, gpjdat) if gpg0 - gpgf7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. register address r/w description reset value gpjcon 0x560000d0 r/w configures the pins of port j 0x0 gpjdat 0x560000d4 r/w the data register for port j undef. gpjup 0x560000d8 r/w pull-up disable register for port j 0x0000 reserved 0x560000dc - - - gpjcon bit description gpj12 [25:24] 00 = input 01 = output 10 = camreset (o) 11 = reserved gpj11 [23:22] 00 = input 01 = output 10 = camclkout(o) 11 = reserved gpj10 [21:20] 00 = input 01 = output 10 =camhref (i) 11 = reserved gpj9 [19:18] 00 = input 01 = output 10 = camvsync] (i) 11 = reserved gpj8 [17:16] 00 = input 01 = output 10 = campclkin] (i) 11 = reserved gpj7 [15:14] 00 = input 01 = output 10 = camdata[7] (i) 11 = reserved gpj6 [13:12] 00 = input 01 = output 10 = camdata[6] (i) 11 = reserved gpj5 [11:10] 00 = input 01 = output 10 = camdata[5] (i) 11 = reserved gpj4 [9:8] 00 = input 01 = output 10 = camdata[4] (i) 11 = reserved gpj3 [7:6] 00 = input 01 = output 10 = camdata[3] (i) 11 = reserved gpj2 [5:4] 00 = input 01 = output 10 = camdata[2] (i) 11 = reserved gpj1 [3:2] 00 = input 01 = output 10 = camdata[1] (i) 11 = reserved gpj0 [1:0] 00 = input 01 = output 10 = camdata[0] (i) 11 = reserved
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-23 gpjdat bit description gpj15:0] [12:0] when the port is configured as an input port, the corresponding bit is the pin state. when the port is configured as an output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. gpjup bit description gpj[12:0] [12:0] 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-24 miscellaneous control register(misccr) in sleep mode, the data bus(d[31:0] or d[15:0] can be set as hi-z and output ?0? state. but, because of the characteristics of io pad, the data bus pull-up resisters have to be turned on or off to reduce the power consumption. d[31:0] pin pull-up resisters can be controlled by misccr register. pads related usb are controlled by this register for usb host, or for usb device. register address r/w description reset value misccr 0x56000080 r/w miscellaneous control register 0x10330 misccr bit description reset value reserved [24] reserveto0. 0 reserved [23] reserveto0. 0 reserved [22] this bit must be 1. 0 battflt_intr [21] batt_flt interrupt on/off. 0: enable 1: disable when 1, battery fault interrupt will be masked by hardware. 0 battflt_func [20] batt_flt function on/off. 0: enable 1: disable when 0, battary fault function will be turned on. 0 offrefresh [19] 0: self refresh retain disable 1: self refresh retain enable when 1, after wake-up from sleep, the self-refresh will be retained. 0 nen_sclk1 [18] sclk0 output enable 0: sclk1 = sclk , 1: sclk1 = 0 0 nen_sclk0 [17] sclk0 output enable 0: sclk0 = sclk , 1: sclk 0 = 0 0 nrstcon [16] nrstout s/w reset 0: nrstout = 0, 1: nrstout = 1 1 reserved [15:14] -00 sel_suspnd1 [13] usb port 1 suspend mode 0 = normal mode 1= suspend mode 0 sel_suspnd0 [12] usb port 0 suspend mode 0 = normal mode 1= suspend mode 0 clksel1 [10:8] 001 = select upll output with clkout0 pad 011 = select hclk with clkout1 pad 100 = select pclk with clkout1 pad 101 = select dclk1 with clkout1 pad 11x = reserved 011
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-25 misccr bit description reset value reserved [7] - 0 clksel0 [6:4] 001 = select upll output with clkout0 pad 011 = select hclk with clkout0 pad 100 = select pclk with clkout0 pad 101 = select dclk0 with clkout0 pad 11x = reserved 011 sel_usbpad [3] usb1 host/device select register. 0=useusb1asdevice 1=useusb1ashost 0 reserved [2] reserved 0 spucr1 [1] 0 = data[31:16] port pull-up resister is enabled 1 = data[31:16] port pull-up resister is disabled 0 spucr0 [0] 0 = data[15:0] port pull-up resister is enabled 1 = data[15:0] port pull-up resister is disabled 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-26 dclk control registers(dclkcon) register address r/w description reset value dclkcon 0x56000084 r/w dclk0/1 control register 0x0 dclkcon bit description dclk1cmp [27:24] dclk1 compare value clock toggle value.( < dclk1div) if the dclk1div is n, low level duration is( n + 1), high level duration is((dclk1div + 1) ?( n +1)) dclk1div [23:20] dclk1 divde value dclk1 frequency = source clock /( dclk1div + 1) dclk1selck [17] select dclk1 source clock 0 = pclk 1 = uclk( usb) dclk1en [16] dclk1 enable 0=dclk1disable 1=dclk1enable dclk0cmp [11:8] dclk0 compare value clock toggle value.( < dclk0div) if the dclk0div is n, low level duration is( n + 1), high level duration is((dclk0div + 1) ?( n +1)) dclk0div [7:4] dclk0 divde value. dclk0 frequency = source clock /( dclk0div + 1) dclk0selck [1] select dclk0 source clock 0 = pclk 1 = uclk( usb) dclk0en [0] dclk0 enable 0=dclk0disable 1=dclk0enable dclkndiv + 1 dclkncmp + 1
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-27 extintn(external interrupt control register n) the 8 external interrupts can be requested by various signaling methods. the extint register configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. to recognize the level interrupt, the valid logic level on extintn pin must be retained for 40ns at least because of the noise filter. register address r/w description reset value extint0 0x56000088 r/w external interrupt control register 0 0x000000 extint1 0x5600008c r/w external interrupt control register 1 0x000000 extint2 0x56000090 r/w external interrupt control register 2 0x000000 extint0 bit description eint7 [30:28] setting the signaling method of the eint7. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint6 [26:24] setting the signaling method of the eint6. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint5 [22:20] setting the signaling method of the eint5. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint4 [18:16] setting the signaling method of the eint4. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint3 [14:12] setting the signaling method of the eint3. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint2 [10:8] setting the signaling method of the eint2. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint1 [6:4] setting the signaling method of the eint1. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint0 [2:0] setting the signaling method of the eint0. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-28 extint1 bit description flten15 [31] filter enable for eint15 0 = filter disable 1= filter enable eint15 [30:28] setting the signaling method of the eint15. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten14 [27] filter enable for eint14 0 = filter disable 1= filter enable eint14 [26:24] setting the signaling method of the eint14. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten13 [23] filter enable for eint13 0 = filter disable 1= filter enable eint13 [22:20] setting the signaling method of the eint13. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten12 [19] filter enable for eint12 0 = filter disable 1= filter enable eint12 [18:16] setting the signaling method of the eint12. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten11 [15] filter enable for eint11 0 = filter disable 1= filter enable eint11 [14:12] setting the signaling method of the eint11. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten10 [11] filter enable for eint10 0 = filter disable 1= filter enable eint10 [10:8] setting the signaling method of the eint10. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten9 [7] filter enable for eint9 0 = filter disable 1= filter enable eint9 [6:4] setting the signaling method of the eint9. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten8 [3] filter enable for eint8 0 = filter disable 1= filter enable eint8 [2:0] setting the signaling method of the eint8. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-29 extint2 bit description reset value flten23 [31] filter enable for eint23 0 = filter disable 1= filter enable 0 eint23 [30:28] setting the signaling method of the eint23. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered 000 flten22 [27] filter enable for eint22 0 = filter disable 1= filter enable 0 eint22 [26:24] setting the signaling method of the eint22. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered 000 flten21 [23] filter enable for eint21 0 = filter disable 1= filter enable 0 eint21 [22:20] setting the signaling method of the eint21. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered 000 flten20 [19] filter enable for eint20 0 = filter disable 1= filter enable 0 eint20 [18:16] setting the signaling method of the eint20. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered 000 flten19 [15] filter enable for eint19 0 = filter disable 1= filter enable 0 eint19 [14:12] setting the signaling method of the eint19. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered 000 flten18 [11] filter enable for eint18 0 = filter disable 1= filter enable 0 eint18 [10:8] setting the signaling method of the eint18. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered 000 flten17 [7] filter enable for eint17 0 = filter disable 1= filter enable 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-30 eint17 [6:4] setting the signaling method of the eint17. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered 000 flten16 [3] filter enable for eint16 0 = filter disable 1= filter enable 0 eint16 [2:0] setting the signaling method of the eint16. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered 000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-31 eintfltn(external interrupt filter register n) to recognize the level interrupt, the valid logic level on extintn pin must be retained for 40ns at least because of the noise filter. register address r/w description reset value eintflt0 0x56000094 r/w reserved 0x000000 eintflt1 0x56000098 r/w reserved 0x000000 eintflt2 0x5600009c r/w external interrupt control register 2 0x000000 eintflt3 0x4c6000a0 r/w external interrupt control register 3 0x000000 eintflt2 bit description eintflt19 [30:24] filtering width of eint19 fltclk18 [23] filter clock of eint18(configured by om) 0 = pclk 1= extclk/osc_clk eintflt18 [22:16] filtering width of eint18 fltclk17 [15] filter clock of eint17(configured by om) 0 = pclk 1= extclk/osc_clk eintflt17 [14:8] filtering width of eint17 fltclk16 [7] filter clock of eint16(configured by om) 0 = pclk 1= extclk/osc_clk eintflt16 [6:0] filtering width of eint16 eintflt3 bit description fltclk23 [31] filter clock of eint23(configured by om) 0 = pclk 1= extclk/osc_clk eintflt23 [30:24] filtering width of eint23 fltclk22 [23] filter clock of eint22(configured by om) 0 = pclk 1= extclk/osc_clk eintflt22 [22:16] filtering width of eint22 fltclk21 [15] filter clock of eint21(configured by om) 0 = pclk 1= extclk/osc_clk eintflt21 [14:8] filtering width of eint21 fltclk20 [7] filter clock of eint20(configured by om) 0 = pclk 1= extclk/osc_clk eintflt20 [6:0] filtering width of eint20
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-32 eintmask(external interrupt mask register) register address r/w description reset value eintmask 0x560000a4 r/w external interupt mask register 0x000fffff eintmask bit description eint23 [23] 0 = enable interrupt 1= masked eint22 [22] 0 = enable interrupt 1= masked eint21 [21] 0 = enable interrupt 1= masked eint20 [20] 0 = enable interrupt 1= masked eint19 [19] 0 = enable interrupt 1= masked eint18 [18] 0 = enable interrupt 1= masked eint17 [17] 0 = enable interrupt 1= masked eint16 [16] 0 = enable interrupt 1= masked eint15 [15] 0 = enable interrupt 1= masked eint14 [14] 0 = enable interrupt 1= masked eint13 [13] 0 = enable interrupt 1= masked eint12 [12] 0 = enable interrupt 1= masked eint11 [11] 0 = enable interrupt 1= masked eint10 [10] 0 = enable interrupt 1= masked eint9 [9] 0 = enable interrupt 1= masked eint8 [8] 0 = enable interrupt 1= masked eint7 [7] 0 = enable interrupt 1= masked eint6 [6] 0 = enable interrupt 1= masked eint5 [5] 0 = enable interrupt 1= masked eint4 [4] 0 = enable interrupt 1= masked reserved [3:0] reserved
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-33 eintpend(external interrupt pending register) register address r/w description reset value eintpend 0x560000a8 r/w external interupt pending register 0x00 eintpend bit description reset value eint23 [23] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint22 [22] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint21 [21] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint20 [20] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint19 [19] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint18 [18] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint17 [17] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint16 [16] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint15 [15] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint14 [14] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint13 [13] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint12 [12] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint11 [11] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint10 [10] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint9 [9] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint8 [8] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint7 [7] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint6 [6] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-34 eint5 [5] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 eint4 [4] it is cleard by writing ?1? 0 = not occur 1= occur interrupt 0 reserved [3:0] reserved 0000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-35 gstatusn (general status registers) register address r/w description reset value gstatus0 0x560000ac r external pin status not define gstatus1 0x560000b0 r/w chip id 0x324100xx gstatus2 0x560000b4 r/w reset status 0x1 gstatus3 0x560000b8 r/w inform register 0x0 gstatus4 0x560000bc r/w inform register 0x0 gstatus0 bit description nwait [3] status of nwait pin ncon [2] status of ncon pin rnb [1] status of rnb pin batt_flt [0] status of batt_flt pin gstatus1 bit description chip id [0] id register = 0x324400-00 gstatus2 bit description reserved [3] reserved wdtrst [2] boot is caused by watch dog reset cleared by writing ?1? sleeprst [1] boot is caused by wakeup reset in sleep mode cleared by writing ?1?. pwrst [0] boot is caused by power on reset cleared by writing ?1? gstatus3 bit description inform [31:0] inform register. this register is cleard by power on reset. otherwise, preserve data value. gstatus4 bit description inform [31:0] inform register. this register is cleard by power on reset. otherwise, preserve data value.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-36 dscn (drive strength control) control the memory i/o drive strength register address r/w description reset value dsc0 0x560000c4 r/w strength control register 0 0x0 dsc1 0x560000c8 r/w strength control register 1 0x0 dsc0 bit description reset value nen_dsc [31] enable drive strength control 0: enable 1: disable 0 reserved [30:10] - 0 dsc_adr [9:8] address bus drive strength. 00: 12ma 01: 10ma 10: 8ma 11: 6ma 00 dsc_data3 [7:6] data[31:24] i/o drive strength. 00: 12ma 01: 10ma 10: 8ma 11: 6ma 00 dsc_data2 [5:4] data[23:16] i/o drive strength. 00: 12ma 01: 10ma 10: 8ma 11: 6ma 00 dsc_data1 [3:2] data[15:8] i/o drive strength. 00: 12ma 01: 10ma 10: 8ma 11: 6ma 00 dsc_data0 [1:0] data[7:0] i/o drive strength. 00: 12ma 01: 10ma 10: 8ma 11: 6ma 00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor i/o ports 9-37 dsc1 bit description reset value dsc_sck1 [29:28] sclk1 drive strength. 00: 12ma 01: 10ma 10: 8ma 11: 6ma 00 dsc_sck0 [27:26] sclk0 drive strength. 00: 16ma 01: 12ma 10: 8ma 11: 6ma 00 dsc_scke [25:24] scke drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_sdr [23:22] nsras/nscas drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_nfc [21:20] nand flash control drive strength( nfce, nfre, nfwe, cle, ale). 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_be [19:18] nbe[3:0] drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_woe [17:16] nwe/noe drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_cs7 [15:14] ngcs7 drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_cs6 [13:12] ngcs6 drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_cs5 [11:10] ngcs5 drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_cs4 [9:8] ngcs4 drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_cs3 [7:6] ngcs3 drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_cs2 [5:4] ngcs2 drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_cs1 [3:2] ngcs1 drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00 dsc_cs0 [1:0] ngcs0 drive strength. 00: 10ma 01: 8ma 10: 6ma 11: 4ma 00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. i/o ports S3C2440X risc microprocessor 9-38 mslcon (memory sleep control register) select memory interface status when in sleep mode. register address r/w description reset value mslcon 0x560000cc r/w memory sleep control register 0x0 dsc0 bit description reset value psc_data [11] data[31:0] pin status in sleep mode. 0: hi-z 1: output ?0?. 0 psc_wait [10] nwait pin status in sleep mode. 0: output ?0? 1: input 0 psc_rnb [9] rnb pin status in sleep mode. 0: output ?0? 1: input 0 psc_nf [8] nand flash i/f pin status in sleep mode( nfce,nfre,nfwe,ale,cle). 0: inactive(nfce,nfre,nfwe,ale,cle = 11100) 1: hi-z 0 psc_sdr [7] nsras, nscas pin status in sleep mode. 0: inactive(?1?) 1: hi-z 0 psc_dqm [6] dqm[3:0]/nwe[3:0] pin status in sleep mode. 0: inactive 1: hi-z 0 psc_oe [5] noe pin status in sleep mode. 0: inactive(?1?) 1: hi-z 0 psc_we [4] nwe pin status in sleep mode. 0: inactive(?1?) 1: hi-z 0 psc_gcs0 [3] ngcs[0] pin status in sleep mode. 0: inactive(?1?) 1: hi-z 0 psc_gcs51 [2] ngcs[5:1] pin status in sleep mode. 0: inactive(?1?) 1: hi-z 0 psc_gcs6 [1] ngcs[6] pin status in sleep mode. 0: inactive(?1?) 1: hi-z 0 psc_gcs7 [0] ngcs[7] pin status in sleep mode. 0: inactive(?1?) 1: hi-z 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor pwm timer 10-1 10 pwm timer overview the S3C2440X has five 16-bit timers. timer 0, 1, 2, and 3 have pulse width modulation (pwm) function. timer 4 has an internal timer only with no output pins. the timer 0 has a dead-zone generator, which is used with a large current device. the timer 0 and 1 share an 8-bit prescaler, while the timer 2, 3 and 4 share other 8-bit prescaler. each timer has a clock divider, which generates 5 different divided signals (1/2, 1/4, 1/8, 1/16, and tclk). each timer block receives its own clock signals from the clock divider, which receives the clock from the corresponding 8-bit prescaler. the 8-bit prescaler is programmable and divides the pclk according to the loading value, which is stored in tcfg0 and tcfg1 registers. the timer count buffer register (tcntbn) has an initial value which is loaded into the down-counter when the timer is enabled. the timer compare buffer register (tcmpbn) has an initial value which is loaded into the compare register to be compared with the down-counter value. this double buffering feature of tcntbn and tcmpbn makes the timer generate a stable output when the frequency and duty ratio are changed. each timer has its own 16-bit down counter, which is driven by the timer clock. when the down counter reaches zero, the timer interrupt request is generated to inform the cpu that the timer operation has been completed. when the timer counter reaches zero, the value of corresponding tcntbn is automatically loaded into the down counter to continue the next operation. however, if the timer stops, for example, by clearing the timer enable bit of tconn during the timer running mode, the value of tcntbn will not be reloaded into the counter. the value of tcmpbn is used for pulse width modulation (pwm). the timer control logic changes the output level when the down-counter value matches the value of the compare register in the timer control logic. therefore, the compare register determines the turn-on time (or turn-off time) of a pwm output. feature ? five 16-bit timers ? two 8-bit prescalers & two 4-bit divider ? programmable duty control of output waveform (pwm) ? auto reload mode or one-shot pulse mode ? dead-zone generator
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. pwm timer S3C2440X risc microprocessor 10-2 clock divider 5:1 mux dead zone generator tout0 tout1 tout2 control logic0 tcmpb0 tcntb0 control logic1 tcmpb1 tcntb1 5:1 mux clock divider 5:1 mux 5:1 mux control logic2 tcmpb2 tcntb2 tout3 control logic3 tcmpb3 tcntb3 no pin pclk 8-bit prescaler 8-bit prescaler dead zone dead zone tclk0 1/8 1/4 1/16 1/2 tclk1 1/8 1/4 1/16 1/2 5:1 mux control logic4 tcntb4 figure 10-1. 16-bit pwm timer block diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor pwm timer 10-3 pwm timer operation prescaler & divider an 8-bit prescaler and a 4-bit divider make the following output frequencies: 4-bit divider settings minimum resolution (prescaler = 0) maximum resolution (prescaler = 255) maximum interval (tcntbn = 65535) 1/2 (pclk = 50 mhz) 0.0400 us (25.0000 mhz) 10.2400 us (97.6562 khz) 0.6710 sec 1/4 (pclk = 50 mhz) 0.0800 us (12.5000 mhz) 20.4800 us (48.8281 khz) 1.3421 sec 1/8 (pclk = 50 mhz) 0.1600 us ( 6.2500 mhz) 40.9601 us (24.4140 khz) 2.6843 sec 1/16 (pclk = 50 mhz) 0.3200 us ( 3.1250 mhz) 81.9188 us (12.2070 khz) 5.3686 sec basic timer operation tcmpn 1 0 tcntn 3 3 2 1 0 2 1 0 0 start bit=1 timer is started tcntn=tcmpn auto-reload tcntn=tcmpn timer is stopped toutn command status tcntbn=3 tcntbn=1 manual update=1 auto-reload=1 tcntbn=2 tcntbn=0 manual update=0 auto-reload=1 interrupt request auto-reload interrupt request figure 10-2. timer operations a timer (except the timer ch-5) has tcntbn, tcntn, tcmpbn and tcmpn. (tcntn and tcmpn are the names of the internal registers. the tcntn register can be read from the tcnton register) the tcntbn and the tcmpbn are loaded into the tcntn and the tcmpn when the timer reaches 0. when the tcntn reaches 0, an interrupt request will occur if the interrupt is enabled.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. pwm timer S3C2440X risc microprocessor 10-4 auto reload & double buffering S3C2440X pwm timers have a double buffering function, enabling the reload value changed for the next timer operation without stopping the current timer operation. so, although the new timer value is set, a current timer operation is completed successfully. the timer value can be written into timer count buffer register (tcntbn) and the current counter value of the timer can be read from timer count observation register (tcnton). if the tcntbn is read, the read value does not indicate the current state of the counter but the reload value for the next timer duration. the auto-reload operation copies the tcntbn into tcntn when the tcntn reaches 0. the value, written into the tcntbn, is loaded to the tcntn only when the tcntn reaches 0 and auto reload is enabled. if the tcntn becomes 0 and the auto reload bit is 0, the tcntn does not operate any further. write tcntbn = 100 write tcntbn = 200 start tcntbn = 150 auto-reload 150 100 100 200 interrupt figure 10-3. example of double buffering function
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor pwm timer 10-5 timer initialization using manual update bit and inverter bit an auto reload operation of the timer occurs when the down counter reaches 0. so, a starting value of the tcntn has to be defined by the user in advance. in this case, the starting value has to be loaded by the manual update bit. the following steps describe how to start a timer: 1) write the initial value into tcntbn and tcmpbn. 2) set the manual update bit of the corresponding timer. it is recommended that you configure the inverter on/off bit. (whether use inverter or not). 3) set start bit of the corresponding timer to start the timer (and clear the manual update bit). if the timer is stopped by force, the tcntn retains the counter value and is not reloaded from tcntbn. if a new value has to be set, perform manual update. note whenever tout inverter on/off bit is changed, the toutn logic value will also be changed whether the timer runs. therefore, it is desirable that the inverter on/off bit is configured with the manual update bit.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. pwm timer S3C2440X risc microprocessor 10-6 timer operation toutn 12 46 50 110 40 40 60 20 3 79 10 5 8 11 figure 10-4. example of a timer operation figure 10-4 shows the result of the following procedure: 1. enable the auto reload function. set the tcntbn to 160 (50+110) and the tcmpbn to 110. set the manual update bit and configure the inverter bit (on/off). the manual update bit sets tcntn and tcmpn to the values of tcntbn and tcmpbn, respectively. and then, set the tcntbn and the tcmpbn to 80 (40+40) and 40, respectively, to determine the next reload value. 2. set the start bit, provided that manual_update is 0 and the inverter is off and auto reload is on. the timer starts counting down after latency time within the timer resolution. 3. when the tcntn has the same value as that of the tcmpn, the logic level of the toutn is changed from low to high. 4. when the tcntn reaches 0, the interrupt request is generated and tcntbn value is loaded into a temporary register. at the next timer tick, the tcntn is reloaded with the temporary register value (tcntbn). 5. in interrupt service routine (isr), the tcntbn and the tcmpbn are set to 80 (20+60) and 60, respectively, for the next duration. 6. when the tcntn has the same value as the tcmpn, the logic level of toutn is changed from low to high. 7. when the tcntn reaches 0, the tcntn is reloaded automatically with the tcntbn, triggering an interrupt request. 8. in interrupt service routine (isr), auto reload and interrupt request are disabled to stop the timer. 9. when the value of the tcntn is same as the tcmpn, the logic level of the toutn is changed from low to high. 10. even when the tcntn reaches 0, the tcntn is not any more reloaded and the timer is stopped because auto reload has been disabled. 11. no more interrupt requests are generated.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor pwm timer 10-7 pulse width modulation (pwm) write tcmpbn = 60 write tcmpbn = 50 write tcmpbn = 40 write tcmpbn = 30 write tcmpbn = 30 write tcmpbn = next pwm value 60 50 40 30 30 figure 10-5. example of pwm pwm function can be implemented by using the tcmpbn. pwm frequency is determined by tcntbn. figure 10-5 shows a pwm value determined by tcmpbn. for a higher pwm value, decrease the tcmpbn value. for a lower pwm value, increase the tcmpbn value. if an output inverter is enabled, the increment/decrement may be reversed. the double buffering function allows the tcmpbn, for the next pwm cycle, written at any point in the current pwm cycle by isr or other routine.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. pwm timer S3C2440X risc microprocessor 10-8 output level control inverter off initial state period 1 period 2 timer stop inverter on figure 10-6. inverter on/off the following procedure describes how to maintain tout as high or low (assume the inverter is off): 1. turn off the auto reload bit. and then, toutn goes to high level and the timer is stopped after the tcntn reaches 0 (recommended). 2. stop the timer by clearing the timer start/stop bit to 0. if tcntn tcmpn, the output level is high .iftcntn >tcmpn, the output level is low . 3. the toutn can be inverted by the inverter on/off bit in tcon. the inverter removes the additional circuit to adjust the output level.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor pwm timer 10-9 dead zone generator the dead zone is for the pwm control in a power device. this function enables the insertion of the time gap between a turn-off of a switching device and a turn on of another switching device. this time gap prohibits the two switching devices from being turned on simultaneously, even for a very short time. tout0 is the pwm output. ntout0 is the inversion of the tout0. if the dead zone is enabled, the output wave form of tout0 and ntout0 will be tout0_dz and ntout0_dz, respectively. ntout0_dz is routed to the tout1 pin. in the dead zone interval, tout0_dz and ntout0_dz can never be turned on simultaneously. tout0 ntout0 tout0_dz ntout0_dz deadzone interval figure 10-7. the wave form when a dead zone feature is enabled
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. pwm timer S3C2440X risc microprocessor 10-10 dma request mode the pwm timer can generate a dma request at every specific time. the timer keeps dma request signals (ndma_req) low until the timer receives an ack signal. when the timer receives the ack signal, it makes the request signal inactive. the timer, which generates the dma request, is determined by setting dma mode bits (in tcfg1 register). if one of timers is configured as dma request mode, that timer does not generate an interrupt request. the others can generate interrupt normally. dma mode configuration and dma / interrupt operation dma mode dma request timer0 int timer1 int timer2 int timer3 int timer4 int 0000 no select on on on on on 0001 timer0 off on on on on 0010 timer1 on off on on on 0011 timer2 on on off on on 0100 timer3 on on on off on 0101 timer4 on on on on off 0110 no select on on on on on pclk int4tmp dmareq_en ndma_ack ndma_req int4 101 figure 10-8. timer4 dma mode operation
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor pwm timer 10-11 pwm timer control registers timer configuration register0 (tcfg0) timer input clock frequency = pclk / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 register address r/w description reset value tcfg0 0x51000000 r/w configures the two 8-bit prescalers 0x00000000 tcfg0 bit description initial state reserved [31:24] 0x00 dead zone length [23:16] these 8 bits determine the dead zone length. the 1 unit time of the dead zone length is equal to that of timer 0. 0x00 prescaler 1 [15:8] these 8 bits determine prescaler value for timer 2, 3 and 4. 0x00 prescaler 0 [7:0] these 8 bits determine prescaler value for timer 0 and 1. 0x00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. pwm timer S3C2440X risc microprocessor 10-12 timer configuration register1 (tcfg1) register address r/w description reset value tcfg1 0x51000004 r/w 5-mux & dma mode selecton register 0x00000000 tcfg1 bit description initial state reserved [31:24] 00000000 dma mode [23:20] select dma request channel 0000 = no select (all interrupt) 0001 = timer0 0010 = timer1 0011 = timer2 0100 = timer3 0101 = timer4 0110 = reserved 0000 mux 4 [19:16] select mux input for pwm timer4. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = external tclk1 0000 mux 3 [15:12] select mux input for pwm timer3. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = external tclk1 0000 mux 2 [11:8] select mux input for pwm timer2. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = external tclk1 0000 mux 1 [7:4] select mux input for pwm timer1. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = external tclk0 0000 mux 0 [3:0] select mux input for pwm timer0. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = external tclk0 0000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor pwm timer 10-13 timer control (tcon) register register address r/w description reset value tcon 0x51000008 r/w timer control register 0x00000000 tcon bit description initial state timer 4 auto reload on/off [22] determine auto reload on/off for timer 4. 0 = one-shot 1 = interval mode (auto reload) 0 timer 4 manual update (note) [21] determine the manual update for timer 4. 0 = no operation 1 = update tcntb4 0 timer 4 start/stop [20] determine start/stop for timer 4. 0 = stop 1 = start for timer 4 0 timer 3 auto reload on/off [19] determine auto reload on/off for timer 3. 0 = one-shot 1 = interval mode (auto reload) 0 timer 3 output inverter on/off [18] determine output inverter on/off for timer 3. 0 = inverter off 1 = inverter on for tout3 0 timer 3 manual update (note) [17] determine manual update for timer 3. 0 = no operation 1 = update tcntb3 & tcmpb3 0 timer 3 start/stop [16] determine start/stop for timer 3. 0 = stop 1 = start for timer 3 0 timer 2 auto reload on/off [15] determine auto reload on/off for timer 2. 0 = one-shot 1 = interval mode (auto reload) 0 timer 2 output inverter on/off [14] determine output inverter on/off for timer 2. 0 = inverter off 1 = inverter on for tout2 0 timer 2 manual update (note) [13] determine the manual update for timer 2. 0 = no operation 1 = update tcntb2 & tcmpb2 0 timer 2 start/stop [12] determine start/stop for timer 2. 0 = stop 1 = start for timer 2 0 timer 1 auto reload on/off [11] determine the auto reload on/off for timer1. 0 = one-shot 1 = interval mode (auto reload) 0 timer 1 output inverter on/off [10] determine the output inverter on/off for timer1. 0 = inverter off 1 = inverter on for tout1 0 timer 1 manual update (note) [9] determine the manual update for timer 1. 0 = no operation 1 = update tcntb1 & tcmpb1 0 timer 1 start/stop [8] determine start/stop for timer 1. 0 = stop 1 = start for timer 1 0 note: the bits have to be cleared at next writing.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. pwm timer S3C2440X risc microprocessor 10-14 tcon (continued) tcon bit description initial state reserved [7:5] reserved dead zone enable [4] determine the dead zone operation. 0 = disable 1 = enable 0 timer 0 auto reload on/off [3] determine auto reload on/off for timer 0. 0 = one-shot 1 = interval mode(auto reload) 0 timer 0 output inverter on/off [2] determine the output inverter on/off for timer 0. 0 = inverter off 1 = inverter on for tout0 0 timer 0 manual update (note) [1] determine the manual update for timer 0. 0 = no operation 1 = update tcntb0 & tcmpb0 0 timer 0 start/stop [0] determine start/stop for timer 0. 0=stop 1=startfortimer0 0 note: the bit have to be cleared at next writing.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor pwm timer 10-15 timer 0 count buffer register & compare buffer register (tcntb0/tcmpb0) register address r/w description reset value tcntb0 0x5100000c r/w timer 0 count buffer register 0x00000000 tcmpb0 0x51000010 r/w timer 0 compare buffer register 0x00000000 tcmpb0 bit description initial state timer 0 compare buffer register [15:0] set compare buffer value for timer 0 0x00000000 tcntb0 bit description initial state timer 0 count buffer register [15:0] set count buffer value for timer 0 0x00000000 timer 0 count observation register (tcnto0) register address r/w description reset value tcnto0 0x51000014 r timer 0 count observation register 0x00000000 tcnto0 bit description initial state timer 0 observation register [15:0] set count observation value for timer 0 0x00000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. pwm timer S3C2440X risc microprocessor 10-16 timer 1 count buffer register & compare buffer register (tcntb1/tcmpb1) register address r/w description reset value tcntb1 0x51000018 r/w timer 1 count buffer register 0x00000000 tcmpb1 0x5100001c r/w timer 1 campare buffer register 0x00000000 tcmpb1 bit description initial state timer 1 compare buffer register [15:0] set compare buffer value for timer 1 0x00000000 tcntb1 bit description initial state timer 1 count buffer register [15:0] set count buffer value for timer 1 0x00000000 timer 1 count observation register (tcnto1) register address r/w description reset value tcnto1 0x51000020 r timer 1 count observation register 0x00000000 tcnto1 bit description initial state timer 1 observation register [15:0] set count observation value for timer 1 0x00000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor pwm timer 10-17 timer 2 count buffer register & compare buffer register (tcntb2/tcmpb2) register address r/w description reset value tcntb2 0x51000024 r/w timer 2 count buffer register 0x00000000 tcmpb2 0x51000028 r/w timer 2 campare buffer register 0x00000000 tcmpb2 bit description initial state timer 2 compare buffer register [15:0] set compare buffer value for timer 2 0x00000000 tcntb2 bit description initial state timer 2 count buffer register [15:0] set count buffer value for timer 2 0x00000000 timer 2 count observation register (tcnto2) register address r/w description reset value tcnto2 0x5100002c r timer 2 count observation register 0x00000000 tcnto2 bit description initial state timer 2 observation register [15:0] set count observation value for timer 2 0x00000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. pwm timer S3C2440X risc microprocessor 10-18 timer 3 count buffer register & compare buffer register (tcntb3/tcmpb3) register address r/w description reset value tcntb3 0x51000030 r/w timer 3 count buffer register 0x00000000 tcmpb3 0x51000034 r/w timer 3 campare buffer register 0x00000000 tcmpb3 bit description initial state timer 3 compare buffer register [15:0] set compare buffer value for timer 3 0x00000000 tcntb3 bit description initial state timer 3 count buffer register [15:0] set count buffer value for timer 3 0x00000000 timer 3 count observation register (tcnto3) register address r/w description reset value tcnto3 0x51000038 r timer 3 count observation register 0x00000000 tcnto3 bit description initial state timer 3 observation register [15:0] set count observation value for timer 3 0x00000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor pwm timer 10-19 timer 4 count buffer register (tcntb4) register address r/w description reset value tcntb4 0x5100003c r/w timer 4 count buffer register 0x00000000 tcntb4 bit description initial state timer 4 count buffer register [15:0] set count buffer value for timer 4 0x00000000 timer 4 count observation register (tcnto4) register address r/w description reset value tcnto4 0x51000040 r timer 4 count observation register 0x00000000 tcnto4 bit description initial state timer 4 observation register [15:0] set count observation value for timer 4 0x00000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. pwm timer S3C2440X risc microprocessor 10-20 notes
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor uart 11-1 11 uart overview the S3C2440X universal asynchronous receiver and transmitter (uart) provide three independent asynchronous serial i/o (sio) ports, each of which can operate in interrupt-based or dma-based mode. in other words,the uart can generate an interrupt or a dma request to transfer data between cpu and the uart. the uart can support bit rates of up to 115.2k bps using system clock. if an external device provides the uart with uartclk, then the uart can operate at higher speed. each uart channel contains two 64-byte fifos for receiver and transmitter. the S3C2440X uart includes programmable baud rates, infrared (ir) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking. each uart contains a baud-rate generator,a transmitter,a receiver and a control unit, as shown in figure 11-1. the baud-rate generator can be clocked by pclk or uartclk. the transmitter and the receiver contain 64-byte fifos and data shifters. data is written to fifo and then copied to the transmit shifter before being transmitted. the data is then shifted out by the transmit data pin (txdn). meanwhile, received data is shifted from the receive data pin (rxdn), and then copied to fifo from the shifter. features ? rxd0, txd0, rxd1, txd1, rxd2,and txd2 with dma-based or interrupt-based operation ? uartch0,1,and2withirda1.0& 64-byte fifo ? uartch0and1withnrts0,ncts0,nrts1,andncts1 ? supports handshake transmit/receive
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. uart S3C2440X risc microprocessor 11-2 block diagram buad-rate generator control unit transmitter receiver peripheral bus txdn clock source rxdn transmit fifo register (fifo mode) transmit holding register (non-fifo mode) receive fifo register (fifo mode) receive holding register (non-fifo mode only) in fifo mode, all 64 byte of buffer register are used as fifo register. in non-fifo mode, only 1 byte of buffer register is used as holding register. transmit shifter transmit buffer register(64 byte) receive shifter receive buffer register(64 byte) figure 11-1 uart block diagram (with fifo)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor uart 11-3 uart operation the following sections describe the uart operations that include data transmission, data reception, interrupt generation, baud-rate generation, loopback mode, infrared mode, and auto flow control. data transmission the data frame for transmission is programmable. it consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ulconn). the transmitter can also produce the break condition, which forces the serial output to logic 0 state for one frame transmission time. this block transmits break signals after the present transmission word is transmitted completely. after the break signal transmission, it continuously transmits data into the tx fifo (tx holding register in the case of non-fifo mode). data reception like the transmission, the data frame for reception is also programmable. it consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits in the line control register (ulconn). the receiver can detect overrun error . the overrun error indicates that new data has overwritten the old data before the old data has been read. receive time-out condition occurs when it does not receive any data during the 3 word time (this interval follows the setting of word length bit) and the rx fifo is not empty in the fifo mode. auto flow control (afc) the S3C2440X's uart 0 and uart 1 support auto flow control with nrts and ncts signals. in case, it can be connected to external uarts. if users want to connect a uart to a modem, disable auto flow control bit in umconn register and control the signal of nrts by software. in afc, nrts depends on the condition of the receiver and ncts signals control the operation of the transmitter. the uart's transmitter transfers the data in fifo only when ncts signals are activated (in afc, ncts means that other uart's fifo is ready to receive data). before the uart receives data, nrts has to be activated when its receive fifo has a spare more than 32-byte and has to be inactivated when its receive fifo has a spare under 32-byte (in afc, nrts means that its own receive fifo is ready to receive data). rxd nrts uart a txd ncts uart b txd ncts uart a rxd nrts uart b transmission case in uart a reception case in uart a figure 11-2 uart afc interface note: uart 2 does not support afc function, because the S3C2440X has no nrts2 and ncts2.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. uart S3C2440X risc microprocessor 11-4 example of non auto-flow control (controlling nrts and ncts by software) rx operation with fifo 1. select receive mode (interrupt or dma mode). 2. check the value of rx fifo count in ufstatn register. if the value is less than 32, users have to set the value of umconn[0] to '1' (activating nrts), and if it is equal or larger than 32 users have to set the value to '0' (inactivating nrts). 3. repeat the step 2. tx operation with fifo 1. select transmit mode (interrupt or dma mode). 2. check the value of umstatn[0]. if the value is '1' (activating ncts), users write the data to tx fifo register.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor uart 11-5 rs-232c interface if users want to connect the uart to modem interface (instead of null modem), nrts, ncts, ndsr, ndtr, dcd and nri signals are needed. in this case, the users can control these signals with general i/o ports by software because the afc does not support the rs-232c interface. interrupt/dma request generation each uart of the S3C2440X has seven status (tx/rx/error) signals: overrun error, receive buffer data ready, transmit buffer empty, and transmit shifter empty, all of which are indicated by the corresponding uart status register (utrstatn/uerstatn). the overrun error can cause the receive error status interrupt request, if the receive-error-status-interrupt-enable bit is set to one in the control register, uconn. when a receive-error-status-interrupt-request is detected, the signal causing the request can be identified by reading the value of uerststn. when the receiver transfers the data of the receive shifter to the receive fifo register in fifo mode and the number of received data reaches rx fifo trigger level, rx interrupt is generated, if receive mode in control register (uconn) is selected as 1 (interrupt request or polling mode). in the non-fifo mode, transferring the data of the receive shifter to the receive holding register will cause rx interrupt under the interrupt request and polling mode. when the transmitter transfers data from its transmit fifo register to its transmit shifter and the number of data left in transmit fifo reaches tx fifo trigger level, tx interrupt is generated, if transmit mode in control register is selected as interrupt request or polling mode. in the non-fifo mode, transferring data from the transmit holding register to the transmit shifter will cause tx interrupt under the interrupt request and polling mode. if the receive mode and transmit mode in control register are selected as the dman request mode then dman request occurs instead of rx or tx interrupt in the situation mentioned above. table 11-1 interrupts in connection with fifo type fifo mode non-fifo mode rx interrupt generated whenever receive data reaches the trigger level of receive fifo. generated when the number of data in fifo does not reaches rx fifo trigger level and does not receive any data during 3 word time (receive time out). this interval follows the setting of word length bit. generated by the receive holding register whenever receive buffer becomes full. tx interrupt generated whenever transmit data reaches the trigger level of transmit fifo (tx fifo trigger level). generated by the transmit holding register whenever transmit buffer becomes empty. error interrupt overrun error will be generated, when it gets to the top of the receive fifo without reading out data in it. overrun error generates an error interrupt immediately.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. uart S3C2440X risc microprocessor 11-6 baud-rate generation each uart's baud-rate generator provides the serial clock for the transmitter and the receiver. the source clock for the baud-rate generator can be selected with the S3C2440X's internal system clock or uartclk. in other words, dividend is selectable by setting clock selection of uconn. the baud-rate clock is generated by dividing thesourceclock(pclkor uartclk ) by 16 and a 16-bit divisor specified in the uart baud-rate divisor register (ubrdivn). the ubrdivn can be determined by the following expression: ubrdivn = (int)(pclk/(bps x16))-1 where, ubrdivn should be from 1 to (2 16 -1). for accurate uart operation, the S3C2440X also supports uartclk as a dividend. if the S3C2440X uses uartclk, which is supplied by an external uart device or system, then the serial clock of uart is exactly synchronized with uartclk. so, the user can get the more precise uart operation. the ubrdivn can be determined: ubrdivn = (int)(uartclk / (bps x 16) ) ?1 where , ubrdivn should be from 1 to (2 16 -1) and uartclk should be smaller than pclk. for example, if the baud-rate is 115200 bps and pclk or uartclk is 40 mhz, ubrdivn is determined: ubrdivn = (int)(40000000/(115200 x 16)) -1 = (int)(21.7) -1 =21-1=20 loopback mode the S3C2440X uart provides a test mode referred to as the loopback mode, to aid in isolating faults in the communication link.this mode structurally enables the connection of rxd and txd in the uart. in this mode, therefore, transmitted data is received to the receiver, via rxd. this feature allows the processor to verify the internal transmit and to receive the data path of each sio channel. this mode can be selected by setting the loopback bit in the uart control register (uconn). break condition the break is defined as a continuous low level signal for one frame transmission time on the transmit data output.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor uart 11-7 infrared (ir) mode the S3C2440X uart block supports infrared (ir) transmission and reception, which can be selected by setting the infrared-mode bit in the uart line control register (ulconn). figure 11-4 illustrates how to implement the ir mode. in ir transmit mode, the transmit pulse comes out at a rate of 3/16, the normal serial transmit rate (when the transmit data bit is zero); in ir receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value (see the frame timing diagrams shown in figure 11-6 and 11-7). irda tx encoder 0 1 0 1 irda rx decoder txd rxd txd irs rxd re uart block figure 11-3. irda function block diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. uart S3C2440X risc microprocessor 11-8 start bit stop bit data bits sio frame 0101001101 figure 11-4. serial i/o frame timing diagram (normal uart) 0 start bit stop bit data bits ir transmit frame bit time pulse width = 3/16 bit frame 00 0 01 1 1 1 1 figure 11-5. infrared transmit mode frame timing diagram 0 start bit stop bit data bits ir receive frame 000 01 1 1 1 1 figure 11-6. infrared receive mode frame timing diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor uart 11-9 uart special registers uart line control register there are three uart line control registers including ulcon0, ulcon1, and ulcon2 in the uart block. register address r/w description reset value ulcon0 0x50000000 r/w uart channel 0 line control register 0x00 ulcon1 0x50004000 r/w uart channel 1 line control register 0x00 ulcon2 0x50008000 r/w uart channel 2 line control register 0x00 ulconn bit description initial state reserved [7] 0 infrared mode [6] determine whether or not to use the infrared mode. 0 = normal mode operation 1 = infrared tx/rx mode 0 parity mode [5:3] specify the type of parity generation and checking during uart transmit and receive operation. 0xx = no parity 100 = odd parity 101 = even parity 110 = parity forced/checked as 1 111 = parity forced/checked as 0 000 number of stop bit [2] specify how many stop bits are to be used for end-of-frame signal. 0=onestopbitperframe 1=twostopbitperframe 0 word length [1:0] indicate the number of data bits to be transmitted or received per frame. 00 = 5-bits 01 = 6-bits 10 = 7-bits 11 = 8-bits 00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. uart S3C2440X risc microprocessor 11-10 uart control register there are three uart control registers including ucon0, ucon1 and ucon2 in the uart block. register address r/w description reset value ucon0 0x50000004 r/w uart channel 0 control register 0x00 ucon1 0x50004004 r/w uart channel 1 control register 0x00 ucon2 0x50008004 r/w uart channel 2 control register 0x00 uconn bit description initial state clock selection [10] select pclk or uartclk for the uart baud rate. 0=pclk : ubrdivn = (int)(pclk / (bps x 16) ) -1 1=uartclk : ubrdivn = (int)(uartclk / (bps x 16) ) -1 0 tx interrupt type [9] interrupt request type. 0 = pulse (interrupt is requested as soon as the tx buffer becomes empty in non-fifo mode or reaches tx fifo trigger level in fifo mode.) 1 = level (interrupt is requested while tx buffer is empty in non-fifo mode or reaches tx fifo trigger level in fifo mode.) 0 rx interrupt type [8] interrupt request type. 0 = pulse (interrupt is requested the instant rx buffer receives the data in non-fifo mode or reaches rx fifo trigger level in fifo mode.) 1 = level (interrupt is requested while rx buffer is receiving data in non-fifo mode or reaches rx fifo trigger level in fifo mode.) 0 rx time out enable [7] enable/disable rx time out interrupt when uart fifo is enabled. the interrupt is a receive interrupt. 0 = disable 1 = enable 0 rx error status interrupt enable [6] this bit enables the uart to generate an interrupt if overrun error occurs during a receive operation 0 = do not generate receive error status interrupt. 1 = generate receive error status interrupt. 0 loopback mode [5] setting loopback bit to 1 causes the uart to enter the loopback mode. this mode is provided for test purposes only. 0 = normal operation 1 = loopback mode 0 send break signal [4] setting this bit causes the uart to send a break during 1 frame time. this bit is automatically cleared after sending the break signal. 0 = normal transmit 1 = send break signal 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor uart 11-11 uart control register (continued) transmit mode [3:2] determine which function is currently able to write tx data to the uart transmit buffer register. (uart tx enable/disable) 00 = disable 01 = interrupt request or polling mode 10 = dma0 request (only for uart0), dma3 request (only for uart2) 11 = dma1 request (only for uart1) 00 receive mode [1:0] determine which function is currently able to read data from uart receive buffer register. (uart rx enable/disable) 00 = disable 01 = interrupt request or polling mode 10 = dma0 request (only for uart0), dma3 request (only for uart2) 11 = dma1 request (only for uart1) 00 note: when the uart does not reach the fifo trigger level and does not receive data during 3 word time in dma receive mode with fifo, the rx interrupt will be generated (receive time out), and the users should check the fifo status and read out the rest.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. uart S3C2440X risc microprocessor 11-12 uart fifo control register there are three uart fifo control registers including ufcon0, ufcon1 and ufcon2 in the uart block. register address r/w description reset value ufcon0 0x50000008 r/w uart channel 0 fifo control register 0x0 ufcon1 0x50004008 r/w uart channel 1 fifo control register 0x0 ufcon2 0x50008008 r/w uart channel 2 fifo control register 0x0 ufconn bit description initial state tx fifo trigger level [7:6] determine the trigger level of transmit fifo. 00 = empty 01 = 16-byte 10 = 32-byte 11 = 48-byte 00 rx fifo trigger level [5:4] determine the trigger level of receive fifo. 00 = 1-byte 01 = 8-byte 10 = 16-byte 11 = 32-byte 00 reserved [3] 0 tx fifo reset [2] auto-cleared after resetting fifo 0 = normal 1= tx fifo reset 0 rx fifo reset [1] auto-cleared after resetting fifo 0 = normal 1= rx fifo reset 0 fifo enable [0] 0 = disable 1 = enable 0 note: when the uart does not reach the fifo trigger level and does not receive data during 3 word time in dma receive mode with fifo, the rx interrupt will be generated (receive time out), and the users should check the fifo status and read out the rest.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor uart 11-13 uart modem control register there are two uart modem control registers including umcon0 and umcon1 in the uart block. register address r/w description reset value umcon0 0x5000000c r/w uart channel 0 modem control register 0x0 umcon1 0x5000400c r/w uart channel 1 modem control register 0x0 reserved 0x5000800c - reserved undef umconn bit description initial state reserved [7:5] these bits must be 0's 00 auto flow control (afc) [4] 0 = disable 1 = enable 0 reserved [3:1] these bits must be 0's 00 request to send [0] if afc bit is enabled, this value will be ignored. in this case the S3C2440X will control nrts automatically. if afc bit is disabled, nrts must be controlled by software. 0 = 'h' level (inactivate nrts) 1 = 'l' level (activate nrts) 0 note: uart 2 does not support afc function, because the S3C2440X has no nrts2 and ncts2.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. uart S3C2440X risc microprocessor 11-14 uart tx/rx status register there are three uart tx/rx status registers including utrstat0, utrstat1 and utrstat2 in the uart block. register address r/w description reset value utrstat0 0x50000010 r uart channel 0 tx/rx status register 0x6 utrstat1 0x50004010 r uart channel 1 tx/rx status register 0x6 utrstat2 0x50008010 r uart channel 2 tx/rx status register 0x6 utrstatn bit description initial state transmitter empty [2] set to 1 automatically when the transmit buffer register has no valid data to transmit and the transmit shift register is empty. 0=notempty 1 = transmitter (transmit buffer & shifter register) empty 1 transmit buffer empty [1] set to 1 automatically when transmit buffer register is empty. 0 =the buffer register is not empty 1=empty (in non-fifo mode, interrupt or dma is requested. in fifo mode, interrupt or dma is requested, when tx fifo trigger level is set to 00 (empty)) if the uart uses the fifo, users should check tx fifo count bits and tx fifo full bit in the ufstat register instead of this bit. 1 receive buffer data ready [0] set to 1 automatically whenever receive buffer register contains valid data, received over the rxdn port. 0=empty 1 = the buffer register has a received data (in non-fifo mode, interrupt or dma is requested) if the uart uses the fifo, users should check rx fifo count bits and rx fifo full bit in the ufstat register instead of this bit. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor uart 11-15 uart error status register there are three uart rx error status registers including uerstat0, uerstat1 and uerstat2 in the uart block. register address r/w description reset value uerstat0 0x50000014 r uart channel 0 rx error status register 0x0 uerstat1 0x50004014 r uart channel 1 rx error status register 0x0 uerstat2 0x50008014 r uart channel 2 rx error status register 0x0 uerstatn bit description initial state overrun error [0] set to 1 automatically whenever an overrun error occurs during receive operation. 0 = no overrun error during receive 1 = overrun error (interrupt is requested.) 0 note: this bit is automatically cleared to 0 when the uart error status register is read.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. uart S3C2440X risc microprocessor 11-16 uart fifo status register there are three uart fifo status registers including ufstat0, ufstat1 and ufstat2 in the uart block. register address r/w description reset value ufstat0 0x50000018 r uart channel 0 fifo status register 0x00 ufstat1 0x50004018 r uart channel 1 fifo status register 0x00 ufstat2 0x50008018 r uart channel 2 fifo status register 0x00 ufstatn bit description initial state reserved [15] 0 tx fifo full [14] set to 1 automatically whenever transmit fifo is full during transmit operation 0=0-byte tx fifo data 63-byte 1=full 0 tx fifo count [13:8] number of data in tx fifo 0 reserved [7] 0 rx fifo full [6] set to 1 automatically whenever receive fifo is full during receive operation 0=0-byte rx fifo data 63-byte 1=full 0 rx fifo count [5:0] number of data in rx fifo 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor uart 11-17 uart modem status register there are two uart modem status registers including umstat0, umstat1 in the uart block. register address r/w description reset value umstat0 0x5000001c r uart channel 0 modem status register 0x0 umstat1 0x5000401c r uart channel 1 modem status register 0x0 reserved 0x5000801c - reserved undef umstat0 bit description initial state reserved [3] 0 delta cts [2] indicate that the ncts input to the S3C2440X has changed state since the last time it was read by cpu. (refer to figure 11-8.) 0 = has not changed 1 = has changed 0 reserved [1] 0 clear to send [0] 0 = cts signal is not activated (ncts pin is high) 1 = cts signal is activated (ncts pin is low) 0 ncts delta cts read_umstat figure 11-7. ncts and delta cts timing diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. uart S3C2440X risc microprocessor 11-18 uart transmit buffer register (holding register & fifo register) there are three uart transmit buffer registers including utxh0, utxh1 and utxh2 in the uart block. utxhn has an 8-bit data for transmission data. register address r/w description reset value utxh0 0x50000020(l) 0x50000023(b) w (by byte) uart channel 0 transmit buffer register - utxh1 0x50004020(l) 0x50004023(b) w (by byte) uart channel 1 transmit buffer register - utxh2 0x50008020(l) 0x50008023(b) w (by byte) uart channel 2 transmit buffer register - utxhn bit description initial state txdatan [7:0] transmit data for uartn - note: (l): the endian mode is little endian. (b): the endian mode is big endian. uart receive buffer register (holding register & fifo register) there are three uart receive buffer registers including urxh0, urxh1 and urxh2 in the uart block. urxhn has an 8-bit data for received data. register address r/w description reset value urxh0 0x50000024(l) 0x50000027(b) r (by byte) uart channel 0 receive buffer register - urxh1 0x50004024(l) 0x50004027(b) r (by byte) uart channel 1 receive buffer register - urxh2 0x50008024(l) 0x50008027(b) r (by byte) uart channel 2 receive buffer register - urxhn bit description initial state rxdatan [7:0] receive data for uartn - note: when an overrun error occurs, the urxhn must be read. if not, the next received data will also make an overrun error, even though the overrun bit of uerstatn had been cleared.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor uart 11-19 uart baud rate divisor register there are three uart baud rate divisor registers including ubrdiv0, ubrdiv1 and ubrdiv2 in the uart block. the value stored in the baud rate divisor register (ubrdivn), is used to determine the serial tx/rx clock rate (baud rate) as follows: ubrdivn = (int)(pclk / (bps x 16) ) ?1 or ubrdivn = (int)( uartclk / (bps x 16) ) ?1 where, the divisor should be from 1 to (2 16 -1) and uartclk should be smaller than pclk. for example, if the baud-rate is 115200 bps and pclk or uartclk is 40 mhz, ubrdivn is: ubrdivn = (int)(40000000 / (115200 x 16) ) -1 = (int)(21.7) -1 =21-1=20 register address r/w description reset value ubrdiv0 0x50000028 r/w baud rate divisior register 0 - ubrdiv1 0x50004028 r/w baud rate divisior register 1 - ubrdiv2 0x50008028 r/w baud rate divisior register 2 - ubrdiv n bit description initial state ubrdiv [15:0] baud rate division value ubrdivn >0 -
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor usb host 12-1 usb host controller overview S3C2440X supports 2-port usb host interface as follows: ? ohci rev 1.0 compatible ? usb rev1.1 compatible ? two down stream ports ? support for both lowspeed and highspeed usb devices hci slave block app_sadr(8) app_sdata(32) hci_data(32) control control ohci regs usb state control list processor block ed&td regs cntl hci master block control ed/td_data(32) ed/td status(32) 64x8 fifo cntl hc_data(8) df_data(8) app_mdata(32) hcm_adr/ data(32) control status control ctrl ctrl rh_data(8) df_data(8) hcf_data(8) addr(6) fifo_data(8) 64x8 fifo root hub & host sie hsie s/m dpll root hub & host sie ohci root hub regs port s/m port s/m port s/m x v r usb 1 x v r usb 2 hci bus ext.fifo status rcf0_regdata(32) txenl txdpls txdmns rcvdata rcvdpls rcvdmns figure 12-1. usb host controller block diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb host s3c2440 x risc microprocessor 12-2 usb host controller special registers the S3C2440X usb cost controller complies with ohci rev 1.0. refer to open host controller interface rev 1.0 specification for detailed information. ohci registers for usb host controller register base address r/w description reset value hcrevision 0x49000000 ? control and status group ? hccontrol 0x49000004 ? ? hccommonstatus 0x49000008 ? ? hcinterruptstatus 0x4900000c ? ? hcinterruptenable 0x49000010 ? ? hcinterruptdisable 0x49000014 ? ? hchcca 0x49000018 ? memory pointer group ? hcperiodcuttented 0x4900001c ? ? hccontrolheaded 0x49000020 ? ? hccontrolcurrented 0x49000024 ? ? hcbulkheaded 0x49000028 ? ? hcbulkcurrented 0x4900002c ? ? hcdonehead 0x49000030 ? ? hcrminterval 0x49000034 ? frame counter group ? hcfmremaining 0x49000038 ? ? hcfmnumber 0x4900003c ? ? hcperiodicstart 0x49000040 ? ? hclsthreshold 0x49000044 ? ? hcrhdescriptora 0x49000048 ? root hub group ? hcrhdescriptorb 0x4900004c ? ? hcrhstatus 0x49000050 ? ? hcrhportstatus1 0x49000054 ? ? hcrhportstatus2 0x49000058 ? ?
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-1 13 usb device controller overview universal serial bus (usb) device controller is designed to provide a high performance full speed function controller solution with dma interface. usb device controller allows bulk transfer with dma, interrupt transfer and control transfer. usb device controller supports: ? full speed usb device controller compatible with the usb specification version 1.1 ? dma interface for bulk transfer ? five endpoints with fifo ep0: 16byte (register) ep1: 128byte in/out fifo (dual port asynchronous ram): interrupt or dma ep2 : 128byte in/out fifo (dual port asynchronous ram): interrupt or dma ep3: 128byte in/out fifo (dual port asynchronous ram): interrupt or dma ep4: 128byte in/out fifo (dual port asynchronous ram): interrupt or dma ? integrated usb transceiver feature ? fully compliant with usb specification version 1.1 ? full speed (12mbps) device ? integrated usb transceiver ? supports control, interrupt and bulk transfer ? five endpoints with fifo: one bi-directional control endpoint with 16-byte fifo (ep0) four bi-directional bulk endpoints with 128-byte fifo (ep1, ep2, ep3, and ep4) ? supports dma interface for receive and transmit bulk endpoints. (ep1, ep2, ep3, and ep4) ? independent 128-byte receive and transmit fifo to maximize throughput ? supports suspend and remote wakeup function
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-2 sie rt_vp_out rt_vm_in rt_vp_in rxd rt_uxsuspend rt_ux_oen rt_vm_out mc_addr[13:0] siu gfi fifos mcu & dma i/f mc_data_in[31:0] mc_data_out[31:0] usb_clk sys_clk sys_resetn mc_wr wr_rdn mc_csn mc_intr dreqn[3:0] dackn[3:0] figure 13-1. usb device controller block diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-3 usb device controller special registers this section describes detailed functionalities about register sets of usb device controller. all special function register is byte-accessible or word-accessible. if you access byte mode offset-address is different in little endian and big endian. all reserved bit is zero. common indexed registers depend on index register (index_reg) (offset address: 0x178) value. for example if you want to write ep0 csr register, you must write ?0x00? on the index_reg before writing in_csr1 register. note. all register must be resettled after performing host reset signaling. register name description offset address non indexed registers func_addr_reg function address register 0x140(l) / 0x143(b) pwr_reg power management register 0x144(l) / 0x147(b) ep_int_reg (ep0?ep4) endpoint interrupt register 0x148(l) / 0x14b(b) usb_int_reg usb interrupt register 0x158(l) / 0x15b(b) ep_int_en_reg (ep0?ep4) endpoint interrupt enable register 0x15c(l) / 0x15f(b) usb_int_en_reg usb interrupt enable register 0x16c(l) / 0x16f(b) frame_num1_reg frame number 1 register 0x170(l) / 0x173(b) frame_num2_reg frame number 2 register 0x174(l) / 0x177(b) index_reg index register 0x178(l) / 0x17b(b) ep0_fifo_reg endpoint0 fifo register 0x1c0(l) / 0x1c3(b) ep1_fifo_reg endpoint1 fifo register 0x1c4(l) / 0x1c7(b) ep2_fifo_reg endpoint2 fifo register 0x1c8(l) / 0x1cb(b) ep3_fifo_reg endpoint3 fifo register 0x1cc(l) / 0x1cf(b) ep4_fifo_reg endpoint4 fifo register 0x1d0(l) / 0x1d3(b) ep1_dma_con endpoint1 dma control register 0x200(l) / 0x203(b) ep1_dma_unit endpoint1 dma unit counter register 0x204(l) / 0x207(b) ep1_dma_fifo endpoint1 dma fifo counter register 0x208(l) / 0x20b(b) ep1_dma_ttc_l endpoint1 dma transfer counter low-byte register 0x20c(l) / 0x20f(b) ep1_dma_ttc_m endpoint1 dma transfer counter middle-byte register 0x210(l) / 0x213(b) ep1_dma_ttc_h endpoint1 dma transfer counter high-byte register 0x214(l) / 0x217(b)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-4 ep2_dma_con endpoint2 dma control register 0x218(l) / 0x21b(b) ep2_dma_unit endpoint2 dma unit counter register 0x21c(l) / 0x21f(b) ep2_dma_fifo endpoint2 dma fifo counter register 0x220(l) / 0x223(b) ep2_dma_ttc_l endpoint2 dma transfer counter low-byte register 0x224(l) / 0x227(b) ep2_dma_ttc_m endpoint2 dma transfer counter middle-byte register 0x228(l) / 0x22b(b) ep2_dma_ttc_h endpoint2 dma transfer counter high-byte register 0x22c(l) / 0x22f(b) ep3_dma_con endpoint3 dma control register 0x240(l) / 0x243(b) ep3_dma_unit endpoint3 dma unit counter register 0x244(l) / 0x247(b) ep3_dma_fifo endpoint3 dma fifo counter register 0x248(l) / 0x24b(b) ep3_dma_ttc_l endpoint3 dma transfer counter low-byte register 0x24c(l) / 0x24f(b) ep3_dma_ttc_m endpoint3 dma transfer counter middle-byte register 0x250(l) / 0x253(b) ep3_dma_ttc_h endpoint3 dma transfer counter high-byte register 0x254(l) / 0x247(b) ep4_dma_con endpoint4 dma control register 0x258(l) / 0x25b(b) ep4_dma_unit endpoint4 dma unit counter register 0x25c(l) / 0x25f(b) ep4_dma_fifo endpoint4 dma fifo counter register 0x260(l) / 0x263(b) ep4_dma_ttc_l endpoint4 dma transfer counter low-byte register 0x264(l) / 0x267(b) ep4_dma_ttc_m endpoint4 dma transfer counter middle-byte register 0x268(l) / 0x26b(b) ep4_dma_ttc_h endpoint4 dma transfer counter high-byte register 0x26c(l) / 0x26f(b) common indexed registers maxp_reg endpoint max packet register 0x18 0 (l) / 0x18 3 (b) in indexed registers in_csr1_reg/ep0_csr ep in control status register 1/ep0 control status register 0x184(l) / 0x187(b) in_csr2_reg ep in control status register 2 0x188(l) / 0x18b(b) out indexed registers out_csr1_reg ep out control status register 1 0x190(l) / 0x193(b) out_csr2_reg ep out control status register 2 0x194(l) / 0x197(b) out_fifo_cnt1_reg ep out write count register 1 0x198(l) / 0x19b(b) out_fifo_cnt2_reg ep out write count register 2 0x19c(l) / 0x19f(b)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-5 function address register (func_addr_reg) this register maintains the usb device controller address assigned by the host. the micro controller unit (mcu) writes the value received through a set_address descriptor to this register. this address is used for the next token. register address r/w description reset value func_addr_reg 0x52000140(l) 0x52000143(b) r/w (byte) function address register 0x00 func_addr_reg bit mcu usb description initial state addr_update [7] r /set r /clear set by the mcu whenever it updates the function_addr field in this register. this bit will be cleared by usb when data_end bit in ep0_csr register. 0 function_addr [6:0] r/w r the mcu write the unique address, assigned by host, to this field. 00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-6 power management register (pwr_reg) this register acts as a power control register in the usb block. register address r/w description reset value pwr_reg 0x52000144(l) 0x52000147(b) r/w (byte) power management register 0x00 pwr_addr bit mcu usb description initial state reserved [7:4] - - - - usb_reset [3] r set set by the usb if reset signaling is received from the host. this bit remains set as long as reset signaling persists on the bus 0 mcu_resume [2] r/w r /clear set by the mcu for mcu resume. the usb generates the resume signaling during 10ms, if this bit is set in suspend mode. suspend_mode [1] r set /clear set by usb automatically when the device enter into suspend mode. it is cleared under the following conditions: 1) the mcu clears the mcu_resume bit by writing ?0?, in order to end remote resume signaling. 2) the resume signal from host is received. 0 suspend_en [0] r/w r suspend mode enable control bit 0 = disable (default). the device will not enter suspend mode. 1 = enable suspend mode 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-7 interrupt register (ep_int_reg/usb_int_reg) the usb core has two interrupt registers. these registers act as status registers for the mcu when it is interrupted. the bits are cleared by writing a ?1? (not ?0?) to each bit that was set. once the mcu is interrupted, mcu should read the contents of interrupt-related registers and write back to clear the contents if it is necessary. register address r/w description reset value ep_int_reg 0x52000148(l) 0x5200014b(b) r/w (byte) ep interrupt pending/clear register 0x00 ep_int_reg bit mcu usb description initial state ep1~ep4 interrupt [4:1] r /clear set for bulk/interrupt in endpoints: set by the usb under the following conditions: 1. in_pkt_rdy bit is cleared. 2. fifo is flushed 3. sent_stall set. for bulk/interrupt out endpoints: set by the usb under the following conditions: 1. sets out_pkt_rdy bit 2. sets sent_stall bit 0 ep0 interrupt [0] r /clear set correspond to endpoint 0 interrupt. set by the usb under the following conditions: 1. out_pkt_rdy bit is set. 2. in_pkt_rdy bit is cleared. 3. sent_stall bit is set 4. setup_end bit is set 5. data_end bit is cleared (it indicates the end of control transfer). 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-8 register address r/w description reset value usb_int_reg 0x52000158(l) 0x5200015b(b) r/w (byte) usb interrupt pending/clear register 0x00 usb_int_reg bit mcu usb description initial state reset interrupt [2] r /clear set set by the usb when it receives reset signaling. 0 resume interrupt [1] r /clear set set by the usb when it receives resume signaling, while in suspend mode. if the resume occurs due to a usb reset, then the mcu is first interrupted with a resume interrupt. once the clocks resume and the se0 condition persists for 3ms, usb reset interrupt will be asserted. 0 suspend interrupt [0] r /clear set set by the usb when it receives suspend signalizing. this bit is set whenever there is no activity for 3ms on the bus. thus, if the mcu does not stop the clock after the first suspend interrupt, it will continue to be interrupted every 3ms as long as there is no activity on the usb bus. by default, this interrupt is disabled. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-9 interrupt enable register (ep_int_en_reg/usb_int_ en_ reg) corresponding to each interrupt register, the usb device controller also has two interrupt enable registers (except resume interrupt enable). by default, usb reset interrupt is enabled. if bit = 0, the interrupt is disabled. if bit = 1, the interrupt is enabled. register address r/w description reset value ep_int_en_reg 0x5200015c(l) 0x5200015f(b) r/w (byte) determine which interrupt is enabled 0xff ep_int_en_reg bit mcu usb description initial state ep4_int_en [4] r/w r ep4 interrupt enable bit 0 = interrupt disable 1 = enable 1 ep3_int_en [3] r/w r ep3 interrupt enable bit 0 = interrupt disable 1 = enable 1 ep2_int_en [2] r/w r ep2 interrupt enable bit 0 = interrupt disable 1 = enable 1 ep1_int_en [1] r/w r ep1 interrupt enable bit 0 = interrupt disable 1 = enable 1 ep0_int_en [0] r/w r ep0 interrupt enable bit 0 = interrupt disable 1 = enable 1
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-10 register address r/w description reset value usb_int_en_reg 0x520016c(l) 0x5200016f(b) r/w (byte) determine which interrupt is enabled 0x04 int_mask_reg bit mcu usb description initial state reset_int_en [2] r/w r reset interrupt enable bit 0 = interrupt disable 1 = enable 1 reserved [1] - - - 0 suspend_int_en [0] r/w r suspend interrupt enable bit 0 = interrupt disable 1 = enable 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-11 frame number register (fpame_num1_reg/frame_num2_reg) when the host transfers usb packets, each start of frame (sof) packit includes a frame number. the usb device controller catches this frame number and loads it into this register automatically. register address r/w description reset value frame_num1_reg 0x52000170(l) 0x52000173(b) r (byte) frame number lower byte register 0x00 frame_num_reg bit mcu usb description initial state frame_num1 [7:0] r w frame number lower byte value 00 register address r/w description reset value frame_num2_reg 0x52000174(l) 0x52000177(b) r (byte) frame number higher byte register 0x00 frame_num_reg bit mcu usb description initial state frame_num2 [7:0] r w frame number higher byte value 00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-12 index register (index_reg) the index register is used to indicate certain endpoint registers effectively. the mcu can access the endpoint registers (maxp_reg, in_csr1_reg, in_csr2_reg, out_csr1_reg, out_csr2_reg, out_fifo_cnt1_reg, and out_fifo_cnt2_reg) for an endpoint inside the core using the index register. register address r/w description reset value index_reg 0x52000178(l) 0x5200017b(b) r/w (byte) register index register 0x00 index_reg bit mcu usb description initial state index [7:0] r/w r indicate a certain endpoint 00 max packet register (maxp_reg) register address r/w description reset value maxp_reg 0x52000180(l) 0x52000183(b) r/w (byte) end point max packet register 0x01 maxp_reg bit mcu usb description initial state maxp [3:0] r/w r 0000: reserved 0001: maxp = 8 byte 0010: maxp = 16 byte 0100: maxp = 32 byte 1000: maxp = 64 byte for ep0, maxp=8 is recommended. for ep1~4, maxp=64 is recommended. and, if maxp=64, the dual packet mode will be enabled automatically. 0001
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-13 end point0 control status register (ep0_csr) this register has the control and status bits for endpoint 0. since a control transaction is involved with both in and out tokens, there is only one csr register, mapped to the in csr1 register. (share in1_csr and can access by writing index register ?0? and read/write in1_csr) register address r/w description reset value ep0_csr 0x52000184(l) 0x52000187(b) r/w (byte) endpoint 0 status register 0x00 ep0_csr bit mcu usb description initial state serviced_se tup_end [7] w clear the mcu should write a "1" to this bit to clear setup_end. 0 serviced_ou t_pkt_rdy [6] w clear the mcu should write a "1" to this bit to clear out_pkt_rdy. 0 send_stall [5] r/w clear mcu should write a "1" to this bit at the same time it clears out_pkt_rdy, if it decodes an invalid token. 0 = finish the stall condition 1 = the usb issues a stall and shake to the current control transfer. 0 setup_end [4] r set set by the usb when a control transfer ends before data_end is set. when the usb sets this bit, an interrupt is generated to the mcu. when such a condition occurs, the usb flushes the fifo and invalidates mcu access to the fifo. 0 data_end [3] set clear set by the mcu on the conditions below: 1. after loading the last packet of data into the fifo, at the same time in_pkt_rdy is set. 2. while it clears out_pkt_rdy after unloading the last packet of data. 3. for a zero length data phase. 0 sent_stall [2] cle ar set set by the usb if a control transaction is stopped due to a protocol violation. an interrupt is generated when this bit is set. the mcu should write "0" to clear this bit. 0 in_pkt_rdy [1] set clear set by the mcu after writing a packet of data into ep0 fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit, so as the mcu to load the next packet. for a zero length data phase, the mcu sets data_end at the same time. 0 out_pkt_rdy [0] r set set by the usb once a valid token is written to the fifo. an interrupt is generated when the usb sets this bit. the mcu clears this bit by writing a "1" to the serviced_out_pkt_rdy bit. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-14 end point in control status register (in_csr1_reg/in_csr2_reg) register address r/w description reset value in_csr1_reg 0x52000184(l) 0x52000187(b) r/w (byte) in end point control status register1 0x00 in_csr1_reg bit mcu usb description initial state reserved [7] - - - 0 clr_data_ toggle [6] r/w r/ clear used in set-up procedure. 0: there are alternation of data0 and data1 1: the data toggle bit is cleared and pid in packet will maintain data0 0 sent_stall [5] r/ clear set set by the usb when an in token issues a stall handshake, after the mcu sets send_stall bit to start stall handshaking. when the usb issues a stall handshake, in_pkt_rdy is cleared 0 send_stall [4] w/r r 0: the mcu clears this bit to finish the stall condition. 1: the mcu issues a stall handshake to the usb. 0 fifo_flush [3] r/w clear set by the mcu if it intends to flush the packet in input-related fifo. this bit is cleared by the usb when the fifo is flushed. the mcu is interrupted when this happens. if a token is in process, the usb waits until the transmission is complete before fifo flushing. if two packets are loaded into the fifo, only first packet (the packet is intended to be sent to the host) is flushed, and the corresponding in_pkt_rdy bit is cleared 0 reserved [2:1] - - - 0 in_pkt_rdy [0 r/set clear set by the mcu after writing a packet of data into the fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit, so the mcu can load the next packet. while this bit is set, the mcu will not be able to write to the fifo. if the mcu sets send stall bit, this bit cannot be set. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-15 register address r/w description reset value in_csr2_reg 0x52000188(l) 0x5200018b(b) r/w (byte) in end point control status register2 0x20 in_csr2_reg bit mcu usb description initial state auto_set [7] r/w r if set, whenever the mcu writes maxp data, in_pkt_rdy will automatically be set by the core without any intervention from mcu. if the mcu writes less than maxp data, in_pkt_rdy bit has to be set by the mcu. 0 iso [6] r/w r used only for endpoints whose transfer type is programmable. 1: reserved 0: configures endpoint to bulk mode 0 mode_in [5] r/w r used only for endpoints whose direction is programmable. 1: configures endpoint direction as in 0: configures endpoint direction as out 1 in_dma_int_en [4] r/w r determine whether the interrupt should be issued or not, when the ep1 in_pkt_rdy condition happens. this is only useful for dma mode. 0 = interrupt enable, 1 = interrupt disable 0 reserved [3:0] - - - -
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-16 end point out control status register (out_csr1_reg/out_csr2_reg) register address r/w description reset value out_csr1_reg 0x52000190(l) 0x52000193(b) r/w (byte) end point out control status register1 0x00 out_csr1_reg bit mcu usb description initial state clr_data_toggle [7] r/w clear when the mcu writes a 1 to this bit, the data toggle sequence bit is reset to data0. 0 sent_stall [6] clear /r set set by the usb when an out token is ended with a stall handshake. the usb issues a stall handshake to the host if it sends more than maxp data for the out token. 0 send_stall [5] r/w r 0: the mcu clears this bit to end the stall condition handshake, in pkt rdy is cleared. 1: the mcu issues a stall handshake to the usb. the mcu clears this bit to end the stall condition handshake, in pkt rdy is cleared. 0 fifo_flush [4] r/w clear the mcu writes a 1 to flush the fifo. this bit can be set only when out_pkt_rdy (d0) is set. the packet due to be unloaded by the mcu will be flushed. 0 reserved [3:1] - - - 0 out_pkt_rdy [0] r/ clear set set by the usb after it has loaded a packet of data into the fifo. once the mcu reads the packet from fifo, this bit should be cleared by mcu (write a "0"). 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-17 register address r/w description reset value out_csr2_reg 0x52000194(l) 0x52000197(b) r/w (byte) end point out control status register2 0x00 out_csr2_reg bit mcu usb description initial state auto_clr [7] r/w r if the mcu is set, whenever the mcu reads data from the out fifo, out_pkt_rdy will automatically be cleared by the logic without any intervention from the mcu. 0 iso [6] r/w r determine endpoint transfer type. 0: configures endpoint to bulk mode. 1: reserved. 0 out_dma_int_mas k [5] r/w r determine whether the interrupt should be issued or not. out_pkt_rdy condition happens. this is only useful for dma mode 0 = interrupt enable 1 = interrupt disable 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-18 end point out write count register (out_fifo_cnt1_reg/out_fifo_cnt2_reg) these registers maintain the number of bytes in the packet as the number is unloaded by the mcu. register address r/w description reset value out_fifo_cnt1_reg 0x52000198(l) 0x5200019b(b) r (byte) end point out write count register1 0x00 out_fifo_cnt1_reg bit mcu usb description initial state out_cnt_low [7:0] r w lower byte of write count 0x00 register address r/w description reset value out_fifo_cnt2_reg 0x5200019c(l) 0x5200019f(b) r (byte) end point out write count register2 0x00 out_fifo_cnt2_reg bit mcu usb description initial state out_cnt_high [7:0] r w higher byte of write count. the out_cnt_high may be always 0 normally. 0x00 end point fifo register (epn_fifo_reg) the epn_fifo_reg enables the mcu to access to the epn fifo. register address r/w description reset value ep0_fifo 0x520001c0(l) 0x520001c3 (b) r/w (byte) end point0 fifo register 0xxx ep1_fifo 0x520001c4(l) 0x520001c7(b) r/w (byte) end point1 fifo register 0xxx ep2_fifo 0x520001c8(l) 0x520001cb(b) r/w (byte) end point2 fifo register 0xxx ep3_fifo 0x520001cc(l) 0x520001cf(b) r/w (byte) end point3 fifo register 0xxx ep4_fifo 0x520001d0(l) 0x520001d3(b) r/w (byte) end point4 fifo register 0xxx epn_fifo bit mcu usb description initial state fifo_data [7:0] r/w r/w fifo data value 0xxx
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-19 dma interface control register (epn_dma_con) register address r/w description reset value ep1_dma_con 0x52000200(l) 0x52000203(b) r/w (byte) ep1 dma interface control register 0x00 ep2_dma_con 0x52000218(l) 0x5200021b(b) r/w (byte) ep2 dma interface control register 0x00 ep3_dma_con 0x52000240(l) 0x52000243(b) r/w (byte) ep3 dma interface control register 0x00 ep4_dma_con 0x52000258(l) 0x5200025b(b) r/w (byte) ep4 dma interface control register 0x00 epn_dma_con bit mcu usb description initial state run_ob [7] r/w w read) dma run observation 0: dma is stopped 1:dma is running write) ignore epn_dma_ttc_n register 0: dma requests will be stopped if epn_dma_ttc_n reaches 0. 1: dma requests will be continued although epn_dma_ttc_n reaches 0. 0 state [6:4] r w dma state monitoring 0 demand_mode [3] r/w r dma demand mode enable bit 0: demand mode disable 1: demand mode enable 0 out_run_ob / out_dma_run [2] r/w r/w functionally separated into write and read operation. write operation: ?0? = stop ?1? = run read operation: out dma run observation 0 in_dma_run [1] r/w r start dma operation. 0=stop 1=run 0 dma_mode_en [0] r/w r/clear set dma mode.if the run_ob has been wrtten as 0 and epn_dma_ttc_n reaches 0, dma_mode_en bit will be cleared by usb. 0 = interrupt mode 1=dmamode 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-20 dma unit counter register (epn_dma_unit) this register is valid in demand mode. in other modes, this register value must be set to ?0x01? register address r/w description reset value ep1_dma_unit 0x52000204(l) 0x52000207(b) r/w (byte) ep1 dma transfer unit counter base register 0x00 ep2_dma_unit 0x5200021c(l) 0x5200021f(b) r/w (byte) ep2 dma transfer unit counter base register 0x00 ep3_dma_unit 0x52000244(l) 0x52000247(b) r/w (byte) ep3 dma transfer unit counter base register 0x00 ep4_dma_unit 0x5200025c(l) 0x5200025f(b) r/w (byte) ep4 dma transfer unit counter base register 0x00 dma_unit bit mcu usb description initial state epn_unit_cnt [7:0] r/w r ep dma transfer unit counter value 0x00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor usb device 13-21 dma fifo counter register (epn_dma_fifo) this register has values in byte size in fifo to be transferred by dma. in case of out_dma_run enabled, the value in out fifo write count register1 will be loaded in this register automatically. in case of in dma mode, the mcu should set proper value by software. register address r/w description reset value ep1_dma_fifo 0x52000208(l) 0x5200020b(b) r/w (byte) ep1 dma transfer fifo counter base register 0x00 ep2_dma_fifo 0x52000220(l) 0x52000223(b) r/w (byte) ep2 dma transfer fifo counter base register 0x00 ep3_dma_fifo 0x52000248(l) 0x5200024b(b) r/w (byte) ep3 dma transfer fifo counter base register 0x00 ep4_dma_fifo 0x52000260(l) 0x52000263(b) r/w (byte) ep4 dma transfer fifo counter base register 0x00 dma_fifo bit mcu usb description initial state epn_fifo_cnt [7:0] r/w r ep dma transfer fifo counter value 0x00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. usb device S3C2440X risc microprocessor 13-22 dma total transfer counter register (epn_dma_ttc_l,m,h) this register should have total number of bytes to be transferred using dma (total 20-bit counter). register address r/w description reset value ep1_dma_ttc_l 0x5200020c(l) 0x5200020f(b) r/w (byte) ep1 dma total transfer counter(lower byte) 0x00 ep1_dma_ttc_m 0x52000210(l) 0x52000213(b) r/w (byte) ep1 dma total transfer counter(middle byte) 0x00 ep1_dma_ttc_h 0x52000214(l) 0x52000217(b) r/w (byte) ep1 dma total transfer counter(higher byte) 0x00 ep2_dma_ttc_l 0x52000224(l) 0x52000227(b) r/w (byte) ep2 dma total transfer counter(lower byte) 0x00 ep2_dma_ttc_m 0x52000228(l) 0x5200022b(b) r/w (byte) ep2 dma total transfer counter(middle byte) 0x00 ep2_dma_ttc_h 0x5200022c(l) 0x5200022f(b) r/w (byte) ep2 dma total transfer counter(higher byte) 0x00 ep3_dma_ttc_l 0x5200024c(l) 0x5200024f(b) r/w (byte) ep3 dma total transfer counter(lower byte) 0x00 ep3_dma_ttc_m 0x52000250(l) 0x52000253(b) r/w (byte) ep3 dma total transfer counter(middle byte) 0x00 ep3_dma_ttc_h 0x52000254(l) 0x52000257(b) r/w (byte) ep3 dma total transfer counter(higher byte) 0x00 ep4_dma_ttc_l 0x52000264(l) 0x52000267(b) r/w (byte) ep4 dma total transfer counter(lower byte) 0x00 ep4_dma_ttc_m 0x52000268(l) 0x5200026b(b) r/w (byte) ep4 dma total transfer counter(middle byte) 0x00 ep4_dma_ttc_h 0x5200026c(l) 0x5200026f(b) r/w (byte) ep4 dma total transfer counter(higher byte) 0x00 dma_tx bit mcu usb description initial state epn_ttc_l [7:0] r/w r dma total transfer count value (lower byte) 0x00 epn_ttc_m [7:0] r/w r dma total transfer count value (middle byte) 0x00 epn_ttc_h [3:0] r/w r dma total transfer count value (higher byte) 0x00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor interrupt controller 14-1 14 interrupt controller overview the interrupt controller in the S3C2440X receives the request from 59 interrupt sources. these interrupt sources are provided by internal peripherals such as the dma controller, the uart, iic, and others. in these interrupt sources, the uartn and eintn interrupts are 'or'ed to the interrupt controller. when receiving multiple interrupt requests from internal peripherals and external interrupt request pins, the interrupt controller requests fiq or irq interrupt of the arm920t core after the arbitration procedure. the arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending register, which helps users notify which interrupt is generated out of various interrupt sources. request sources (with sub -register) request sources (without sub -register) srcpnd mask mode priority intpnd irq fiq subsrcpnd submask lcd interrupt has different features. please see the chapter 15 lcd controller figure 14-1. interrupt process diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. interrupt controller S3C2440X risc microprocessor 14-2 interrupt controller operation f-bit and i-bit of program status register (psr) if the f-bit of psr in arm920t cpu is set to 1, the cpu does not accept the fast interrupt request (fiq) from the interrupt controller. likewise, if i-bit of the psr is set to 1, the cpu does not accept the interrupt request (irq) from the interrupt controller. so, the interrupt controller can receive interrupts by clearing f-bit or i-bit of the psr to 0 and setting the corresponding bit of intmsk to 0. interrupt mode the arm920t has two types of interrupt mode: fiq or irq. all the interrupt sources determine which mode is used at interrupt request. interrupt pending register the S3C2440X has two interrupt pending resisters: source pending register (srcpnd) and interrupt pending register (intpnd). these pending registers indicate whether or not an interrupt request is pending. when the interrupt sources request interrupt service, the corresponding bits of srcpnd register are set to 1, and at the same time, only one bit of the intpnd register is set to 1 automatically after arbitration procedure. if interrupts are masked, the corresponding bits of the srcpnd register are set to 1. this does not cause the bit of intpnd register changed. when a pending bit of the intpnd register is set, the interrupt service routine starts whenever the i-flag or f-flag is cleared to 0. the srcpnd and intpnd registers can be read and written, so the service routine must clear the pending condition by writin ga1tothecorrespondingbitinthesrcpndregisterfirstand then clear the pending condition in the intpnd registers by using the same method. interrupt mask register this register indicates that an interrupt has been disabled if the corresponding mask bit is set to 1. if an interrupt mask bit of intmsk is 0, the interrupt will be serviced normally. if the corresponding mask bit is 1 and the interrupt is generated, the source pending bit will be set.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor interrupt controller 14-3 interrupt sources the interrupt controller supports 59 interrupt sources as shown in the table below. sources descriptions arbiter group int_adc adc eoc and touch interrupt (int_adc/int_tc) arb5 int_rtc rtc alarm interrupt arb5 int_spi1 spi1 interrupt arb5 int_uart0 uart0 interrupt (err, rxd, and txd) arb5 int_iic iic interrupt arb4 int_usbh usb host interrupt arb4 int_usbd usb device interrupt arb4 int_nfcon nand flash control interrupt arb4 int_uart1 uart1 interrupt (err, rxd, and txd) arb4 int_spi0 spi0 interrupt arb4 int_sdi sdi interrupt arb 3 int_dma3 dma channel 3 interrupt arb3 int_dma2 dma channel 2 interrupt arb3 int_dma1 dma channel 1 interrupt arb3 int_dma0 dma channel 0 interrupt arb3 int_lcd lcd interrupt (int_frsyn and int_ficnt) arb3 int_uart2 uart2 interrupt (err, rxd, and txd) arb2 int_timer4 timer4 interrupt arb2 int_timer3 timer3 interrupt arb2 int_timer2 timer2 interrupt arb2 int_timer1 timer1 interrupt arb 2 int_timer0 timer0 interrupt arb2 int_wdt watch-dog timer interrupt arb1 int_tick rtc time tick interrupt arb1 nbatt_flt battery fault interrupt arb1 int_cam camera interface (int_cam_s, int_cam_c) arb1 eint8_23 external interrupt 8 ? 23 arb1 eint4_7 external interrupt 4 ? 7 arb1 eint3 external interrupt 3 arb0 eint2 external interrupt 2 arb0 eint1 external interrupt 1 arb0 eint0 external interrupt 0 arb0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. interrupt controller S3C2440X risc microprocessor 14-4 interrupt priority generating block the priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in figure 14-1 below. arbiter6 arbiter0 arm irq req1/eint0 arbiter1 arbiter2 arbiter3 arbiter4 arbiter5 req4/int_tick req5/int_wdt req0/int_timer0 req3/int_timer3 req2/int_timer2 req1/int_timer1 req4/int_timer4 req0/int_lcd req1/int_dma0 req3/int_dma2 req2/int_dma1 req5/int_uart2 req4/int_dma3 req5/int_sdi req0/int_spi0 req1/int_uart1 req2/int_nfcon req3/int_usbd req4/int_usbh req5/int_iic req1/int_uart0 req2/int_spi1 req3/int_rtc req4/int_adc req0 req1 req2 req3 req4 req5 req2/eint1 req3/eint2 req4/eint3 req0/eint4_7 req1/eint8_23 req2/int_cam req3/nbatt_flt figure 14-2. priority generating block
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor interrupt controller 14-5 interrupt priority each arbiter can handle six interrupt requests based on the one bit arbiter mode control (arb_mode) and two bits of selection control signals (arb_sel) as follows: if arb_sel bits are 00b, the priority order is req0, req1, req2, req3, req4, and req5. if arb_sel bits are 01b, the priority order is req0, req2, req3, req4, req1, and req5. if arb_sel bits are 10b, the priority order is req0, req3, req4, req1, req2, and req5. if arb_sel bits are 11b, the priority order is req0, req4, req1, req2, req3, and req5. note that req0 of an arbiter always has the highest priority, and req5 has the lowest one. in addition, by changing the arb_sel bits, we can rotate the priority of req1 to req4. here, if arb_mode bit is set to 0, arb_sel bits are not automatically changed, making the arbiter to operate in the fixed priority mode (note that even in this mode, we can reconfigure the priority by manually changing the arb_sel bits). on the other hand, if arb_mode bit is 1, arb_sel bits are changed in rotation fashion, e.g., if req1 is serviced, arb_sel bits are changed to 01b automatically so as to put req1 into the lowest priority. the detailed rules of arb_sel change are as follows: if req0 or req5 is serviced, arb_sel bits are not changed at all. if req1 is serviced, arb_sel bits are changed to 01b. if req2 is serviced, arb_sel bits are changed to 10b. if req3 is serviced, arb_sel bits are changed to 11b. if req4 is serviced, arb_sel bits are changed to 00b.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. interrupt controller S3C2440X risc microprocessor 14-6 interrupt controller special registers there are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. all the interrupt requests from the interrupt sources are first registered in the source pending register. they are divided into two groups including fast interrupt request (fiq) and interrupt request (irq), based on the interrupt mode register. the arbitration procedure for multiple irqs is based on the priority register. source pending (srcpnd) register the srcpnd register is composed of 32 bits each of which is related to an interrupt source. each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. accordingly, this register indicates which interrupt source is waiting for the request to be serviced. note that each bit of the srcpnd register is automatically set by the interrupt sources regardless of the masking bits in the intmask register. in addition, the srcpnd register is not affected by the priority logic of interrupt controller. in the interrupt service routine for a specific interrupt source, the corresponding bit of the srcpnd register has to be cleared to get the interrupt request from the same source correctly. if you return from the isr without clearing the bit, the interrupt controller operates as if another interrupt request came in from the same source. in other words, if a specific bit of the srcpnd register is set to 1, it is always considered as a valid interrupt request waiting to be serviced. the time to clear the corresponding bit depends on the user's requirement. if you want to receive another valid request from the same source, you should clear the corresponding bit first, and then enable the interrupt. you can clear a specific bit of the srcpnd register by writing a data to this register. it clears only the bit positions of the srcpnd corresponding to those set to one in the data. the bit positions corresponding to those that are set to 0 in the data remains as they are. register address r/w description reset value srcpnd 0x4a000000 r/w indicate the interrupt request status. 0 = the interrupt has not been requested. 1 = the interrupt source has asserted the interrupt request. 0x00000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor interrupt controller 14-7 srcpnd bit description initial state int_adc [31] 0 = not requested, 1 = requested 0 int_rtc [30] 0 = not requested, 1 = requested 0 int_spi1 [29] 0 = not requested, 1 = requested 0 int_uart0 [28] 0 = not requested, 1 = requested 0 int_iic [27] 0 = not requested, 1 = requested 0 int_usbh [26] 0 = not requested, 1 = requested 0 int_usbd [25] 0 = not requested, 1 = requested 0 int_nfcon [24] 0 = not requested, 1 = requested 0 int_uart1 [23] 0 = not requested, 1 = requested 0 int_spi0 [22] 0 = not requested, 1 = requested 0 int_sdi [21] 0 = not requested, 1 = requested 0 int_dma3 [20] 0 = not requested, 1 = requested 0 int_dma2 [19] 0 = not requested, 1 = requested 0 int_dma1 [18] 0 = not requested, 1 = requested 0 int_dma0 [17] 0 = not requested, 1 = requested 0 int_lcd [16] 0 = not requested, 1 = requested 0 int_uart2 [15] 0 = not requested, 1 = requested 0 int_timer4 [14] 0 = not requested, 1 = requested 0 int_timer3 [13] 0 = not requested, 1 = requested 0 int_timer2 [12] 0 = not requested, 1 = requested 0 int_timer1 [11] 0 = not requested, 1 = requested 0 int_timer0 [10] 0 = not requested, 1 = requested 0 int_wdt [9] 0 = not requested, 1 = requested 0 int_tick [8] 0 = not requested, 1 = requested 0 nbatt_flt [7] 0 = not requested, 1 = requested 0 int_cam [6] 0 = not requested, 1 = requested 0 eint8_23 [5] 0 = not requested, 1 = requested 0 eint4_7 [4] 0 = not requested, 1 = requested 0 eint3 [3] 0 = not requested, 1 = requested 0 eint2 [2] 0 = not requested, 1 = requested 0 eint1 [1] 0 = not requested, 1 = requested 0 eint0 [0] 0 = not requested, 1 = requested 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. interrupt controller S3C2440X risc microprocessor 14-8 . interrupt mode (intmod) register this register is composed of 32 bits each of which is related to an interrupt source. if a specific bit is set to 1, the corresponding interrupt is processed in the fiq (fast interrupt) mode. otherwise, it is processed in the irq mode (normal interrupt). note that only one interrupt source can be serviced in the fiq mode in the interrupt controller (you should use the fiq mode only for the urgent interrupt). thus, only one bit of intmod can be set to 1. register address r/w description reset value intmod 0x4a000004 r/w interrupt mode regiseter. 0 = irq mode 1 = fiq mode 0x00000000 note : if an interrupt mode is set to fiq mode in the intmod register, fiq interrupt will not affect both intpnd and intoffset registers. in this case, the two registers are valid only for irq mode interrupt source.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor interrupt controller 14-9 intmod bit description initial state int_adc [31] 0 = irq, 1 = fiq 0 int_rtc [30] 0 = irq, 1 = fiq 0 int_spi1 [29] 0 = irq, 1 = fiq 0 int_uart0 [28] 0 = irq, 1 = fiq 0 int_iic [27] 0 = irq, 1 = fiq 0 int_usbh [26] 0 = irq, 1 = fiq 0 int_usbd [25] 0 = irq, 1 = fiq 0 int_nfcon [24] 0 = irq, 1 = fiq 0 int_urrt1 [23] 0 = irq, 1 = fiq 0 int_spi0 [22] 0 = irq, 1 = fiq 0 int_sdi [21] 0 = irq, 1 = fiq 0 int_dma3 [20] 0 = irq, 1 = fiq 0 int_dma2 [19] 0 = irq, 1 = fiq 0 int_dma1 [18] 0 = irq, 1 = fiq 0 int_dma0 [17] 0 = irq, 1 = fiq 0 int_lcd [16] 0 = irq, 1 = fiq 0 int_uart2 [15] 0 = irq, 1 = fiq 0 int_timer4 [14] 0 = irq, 1 = fiq 0 int_timer3 [13] 0 = irq, 1 = fiq 0 int_timer2 [12] 0 = irq, 1 = fiq 0 int_timer1 [11] 0 = irq, 1 = fiq 0 int_timer0 [10] 0 = irq, 1 = fiq 0 int_wdt [9] 0 = irq, 1 = fiq 0 int_tick [8] 0 = irq, 1 = fiq 0 nbatt_flt [7] 0=irq, 1=fiq 0 int_cam [6] 0 = irq, 1 = fiq 0 eint8_23 [5] 0 = irq, 1 = fiq 0 eint4_7 [4] 0 = irq, 1 = fiq 0 eint3 [3] 0=irq, 1=fiq 0 eint2 [2] 0=irq, 1=fiq 0 eint1 [1] 0=irq, 1=fiq 0 eint0 [0] 0=irq, 1=fiq 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. interrupt controller S3C2440X risc microprocessor 14-10 interrupt mask (intmsk) register this register also has 32 bits each of which is related to an interrupt source. if a specific bit is set to 1, the cpu does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of srcpnd register is set to 1). if the mask bit is 0, the interrupt request can be serviced. register address r/w description reset value intmsk 0x4a000008 r/w determine which interrupt source is masked. the masked interrupt source will not be serviced. 0 = interrupt service is available. 1 = interrupt service is masked. 0xffffffff
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor interrupt controller 14-11 intmsk bit description initial state int_adc [31] 0 = service available, 1 = masked 1 int_rtc [30] 0 = service available, 1 = masked 1 int_spi1 [29] 0 = service available, 1 = masked 1 int_uart0 [28] 0 = service available, 1 = masked 1 int_iic [27] 0 = service available, 1 = masked 1 int_usbh [26] 0 = service available, 1 = masked 1 int_usbd [25] 0 = service available, 1 = masked 1 int_nfcon [24] 0 = service available, 1 = masked 1 int_uart1 [23] 0 = service available, 1 = masked 1 int_spi0 [22] 0 = service available, 1 = masked 1 int_sdi [21] 0 = service available, 1 = masked 1 int_dma3 [20] 0 = service available, 1 = masked 1 int_dma2 [19] 0 = service available, 1 = masked 1 int_dma1 [18] 0 = service available, 1 = masked 1 int_dma0 [17] 0 = service available, 1 = masked 1 int_lcd [16] 0 = service available, 1 = masked 1 int_uart2 [15] 0 = service available, 1 = masked 1 int_timer4 [14] 0 = service available, 1 = masked 1 int_timer3 [13] 0 = service available, 1 = masked 1 int_timer2 [12] 0 = service available, 1 = masked 1 int_timer1 [11] 0 = service available, 1 = masked 1 int_timer0 [10] 0 = service available, 1 = masked 1 int_wdt [9] 0 = service available, 1 = masked 1 int_tick [8] 0 = service available, 1 = masked 1 nbatt_flt [7] 0 = service available, 1 = masked 1 int_cam [6] 0 = service available, 1 = masked 1 eint8_23 [5] 0 = service available, 1 = masked 1 eint4_7 [4] 0 = service available, 1 = masked 1 eint3 [3] 0 = service available, 1 = masked 1 eint2 [2] 0 = service available, 1 = masked 1 eint1 [1] 0 = service available, 1 = masked 1 eint0 [0] 0 = service available, 1 = masked 1
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. interrupt controller S3C2440X risc microprocessor 14-12 priority register (priority) register address r/w description reset value priority 0x4a00000c r/w irq priority control register 0x7f priority bit description initial state arb_sel6 [20:19] arbiter 6 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel5 [18:17] arbiter 5 group priority order set 00 = req 1-2-3-4 01 = req 2-3-4-1 10 = req 3-4-1-2 11 = req 4-1-2-3 0 arb_sel4 [16:15] arbiter 4 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel3 [14:13] arbiter 3 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel2 [12:11] arbiter 2 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel1 [10:9] arbiter 1 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel0 [8:7] arbiter 0 group priority order set 00 = req 1-2-3-4 01 = req 2-3-4-1 10 = req 3-4-1-2 11 = req 4-1-2-3 0 arb_mode6 [6] arbiter 6 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode5 [5] arbiter 5 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode4 [4] arbiter 4 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode3 [3] arbiter 3 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode2 [2] arbiter 2 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode1 [1] arbiter 1 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode0 [0] arbiter 0 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor interrupt controller 14-13 interrupt pending (intpnd) register each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority . since the intpnd register is located after the priority logic, only one bit can be set to 1, and that interrupt request generates irq to cpu. in interrupt service routine for irq, you can read this register to determine which interrupt source is serviced among the 32 sources. like the srcpnd register, this register has to be cleared in the interrupt service routine after clearing the srcpnd register. we can clear a specific bit of the intpnd register by writing a data to this register. it clears only the bit positions of the intpnd register corresponding to those set to one in the data. the bit positions corresponding to those that are set to 0 in the data remains as they are. register address r/w description reset value intpnd 0x4a000010 r/w indicate the interrupt request status. 0 = the interrupt has not been requested. 1 = the interrupt source has asserted the interrupt request. 0x00000000 note : if the fiq mode interrupt occurs, the corresponding bit of intpnd will not be turned on as the intpnd register is available only for irq mode interrupt.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. interrupt controller S3C2440X risc microprocessor 14-14 intpnd bit description initial state int_adc [31] 0 = not requested, 1 = requested 0 int_rtc [30] 0 = not requested, 1 = requested 0 int_spi1 [29] 0 = not requested, 1 = requested 0 int_uart0 [28] 0 = not requested, 1 = requested 0 int_iic [27] 0 = not requested, 1 = requested 0 int_usbh [26] 0 = not requested, 1 = requested 0 int_usbd [25] 0 = not requested, 1 = requested 0 int_nfcon [24] 0 = not requested, 1 = requested 0 int_uart1 [23] 0 = not requested, 1 = requested 0 int_spi0 [22] 0 = not requested, 1 = requested 0 int_sdi [21] 0 = not requested, 1 = requested 0 int_dma3 [20] 0 = not requested, 1 = requested 0 int_dma2 [19] 0 = not requested, 1 = requested 0 int_dma1 [18] 0 = not requested, 1 = requested 0 int_dma0 [17] 0 = not requested, 1 = requested 0 int_lcd [16] 0 = not requested, 1 = requested 0 int_uart2 [15] 0 = not requested, 1 = requested 0 int_timer4 [14] 0 = not requested, 1 = requested 0 int_timer3 [13] 0 = not requested, 1 = requested 0 int_timer2 [12] 0 = not requested, 1 = requested 0 int_timer1 [11] 0 = not requested, 1 = requested 0 int_timer0 [10] 0 = not requested, 1 = requested 0 int_wdt [9] 0 = not requested, 1 = requested 0 int_tick [8] 0 = not requested, 1 = requested 0 nbatt_flt [7] 0 = not requested, 1 = requested 0 int_cam [6] 0 = not requested, 1 = requested 0 eint8_23 [5] 0 = not requested, 1 = requested 0 eint4_7 [4] 0 = not requested, 1 = requested 0 eint3 [3] 0 = not requested, 1 = requested 0 eint2 [2] 0 = not requested, 1 = requested 0 eint1 [1] 0 = not requested, 1 = requested 0 eint0 [0] 0 = not requested, 1 = requested 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor interrupt controller 14-15 interrupt offset (intoffset) register the value in the interrupt offset register shows which interrupt request of irq mode is in the intpnd register. this bit can be cleared automatically by clearing srcpnd and intpnd. register address r/w description reset value intoffset 0x4a000014 r indicate the irq interrupt request source 0x00000000 int source the offset value int source the offset value int_adc 31 int_uart2 15 int_rtc 30 int_timer4 14 int_spi1 29 int_timer3 13 int_uart0 28 int_timer2 12 int_iic 27 int_timer1 11 int_usbh 26 int_timer0 10 int_usbd 25 int_wdt 9 int_nfcon 24 int_tick 8 int_uart1 23 nbatt_flt 7 int_spi0 22 int_cam 6 int_sdi 21 eint8_23 5 int_dma3 20 eint4_7 4 int_dma2 19 eint3 3 int_dma1 18 eint2 2 int_dma0 17 eint1 1 int_lcd 16 eint0 0 note : fiq mode interrupt does not affect the intoffset register as the register is available only for irq mode interrupt.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. interrupt controller S3C2440X risc microprocessor 14-16 sub source pending (subsrcpnd) register you can clear a specific bit of the subsrcpnd register by writing a data to this register. it clears only the bit positions of the subsrcpnd register corresponding to those set to one in the data. the bit positions corresponding to those that are set to 0 in the data remains as they are. register address r/w description reset value subsrcpnd 0x4a000018 r/w indicate the interrupt request status. 0 = the interrupt has not been requested. 1 = the interrupt source has asserted the interrupt request. 0x00000000 subsrcpnd bit description initial state reserved [31:13] not used 0 int_cam_c [12] 0 = not requested, 1 = requested 0 int_cam_s [11] 0 = not requested, 1 = requested 0 int_adc [10] 0 = not requested, 1 = requested 0 int_tc [9] 0 = not requested, 1 = requested 0 int_err2 [8] 0 = not requested, 1 = requested 0 int_txd2 [7] 0 = not requested, 1 = requested 0 int_rxd2 [6] 0 = not requested, 1 = requested 0 int_err1 [5] 0 = not requested, 1 = requested 0 int_txd1 [4] 0 = not requested, 1 = requested 0 int_rxd1 [3] 0 = not requested, 1 = requested 0 int_err0 [2] 0 = not requested, 1 = requested 0 int_txd0 [1] 0 = not requested, 1 = requested 0 int_rxd0 [0] 0 = not requested, 1 = requested 0 map to srcpnd srcpnd subsrcpnd remark int_uart0 int_rxd0,int_txd0,int_err0 int_uart1 int_rxd1,int_txd1,int_err1 int_uart2 int_rxd2,int_txd2,int_err2 int_adc int_adc, int_tc int_cam int_cam_s, int_cam_c
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor interrupt controller 14-17 interrupt sub mask (intsubmsk) register this register has 11 bits each of which is related to an interrupt source. if a specific bit is set to 1, the interrupt request from the corresponding interrupt source is not serviced by the cpu (note that even in such a case, the corresponding bit of the subsrcpnd register is set to 1). if the mask bit is 0, the interrupt request can be serviced. register address r/w description reset value intsubmsk 0x4a00001c r/w determine which interrupt source is masked. the masked interrupt source will not be serviced. 0 = interrupt service is available. 1 = interrupt service is masked. 0xffff intsubmsk bit description initial state reserved [31:16] not used 0 reserved [15:13] not used 0x7 int_cam_c [12] 0 = service available, 1 = masked 1 int_cam_s [11] 0 = service available, 1 = masked 1 int_adc [10] 0 = service available, 1 = masked 1 int_tc [9] 0 = service available, 1 = masked 1 int_err2 [8] 0 = service available, 1 = masked 1 int_txd2 [7] 0 = service available, 1 = masked 1 int_rxd2 [6] 0 = service available, 1 = masked 1 int_err1 [5] 0 = service available, 1 = masked 1 int_txd1 [4] 0 = service available, 1 = masked 1 int_rxd1 [3] 0 = service available, 1 = masked 1 int_err0 [2] 0 = service available, 1 = masked 1 int_txd0 [1] 0 = service available, 1 = masked 1 int_rxd0 [0] 0 = service available, 1 = masked 1
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. interrupt controller S3C2440X risc microprocessor 14-18 notes
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-1 15 lcd controller overview the lcd controller in the S3C2440X consists of the logic for transferring lcd image data from a video buffer locatedinsystemmemorytoanexternallcddriver. the lcd controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level gray scale) mode on a monochrome lcd, using a time-based dithering algorithm and frame rate control (frc) method and it can be interfaced with a color lcd panel at 8-bit per pixel (256-level color) and 12-bit per pixel (4096-level color) for interfacing with stn lcd. it can support 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, and 8-bit per pixel for interfacing with the palettized tft color lcd panel, and 16-bit per pixel and 24-bit per pixel for non-palettized true-color display. the lcd controller can be programmed to support different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate. features stn lcd displays: ? supports 3 types of lcd panels: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display type ? supports the monochrome, 4 gray levels, and 16 gray levels ? supports 256 colors and 4096 colors for color stn lcd panel ? supports multiple screen size typical actual screen size: 640 x 480, 320 x 240, 160 x 160, and others maximum virtual screen size is 4mbytes. maximum virtual screen size in 256 color mode: 4096 x 1024, 2048 x 2048, 1024 x 4096, and others tft lcd displays: ? supports 1, 2, 4 or 8-bpp (bit per pixel) palettized color displays for tft ? supports 16-bpp non-palettized true-color displays for color tft ? supports 24-bpp non-palettized true-color displays for color tft ? supports maximum 16m color tft at 24bit per pixel mode ? supports multiple screen size typical actual screen size: 640 x 480, 320 x 240, 160 x 160, and others maximum virtual screen size is 4mbytes. maximum virtual screen size in 64k color mode: 2048 x 1024 and others
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-2 common features the lcd controller has a dedicated dma that supports to fetch the image data from video buffer located in system memory. its features also include: ? dedicated interrupt functions (int_frsyn and int_ficnt) ? the system memory is used as the display memory. ? supports multiple virtual display screen (supports hardware horizontal/vertical scrolling) ? programmable timing control for different display panels ? supports little and big-endian byte ordering, as well as wince data formats ? supports 2-type sec tft lcd panel (samsung 3.5? portrait / 256k color /reflective and transflective a-si tft lcd) lts350q1-pd1: tft lcd panel with touch panel and front light unit (reflective type) lts350q1-pd2: tft lcd panel only lts350q1-pe1: tft lcd panel with touch panel and front light unit (transflective type) lts350q1-pe2: tft lcd panel only note wince doesn?t support the 12-bit packed data format. please check if wince can support the 12-bit color-mode. external interface signal stn tft sec tft (lts350q1-pd1/2) sec tft (lts350q1-pe1/2) vframe (frame sync. signal) vsync (vertical sync. signal) stv stv vline (line sync pulse signal) hsync (horizontal sync. signal) cpv cpv vclk (pixel clock signal ) vclk (pixel clock signal ) lcd_hclk lcd_hclk vd[23:0] (lcd pixel data output ports) vd[23:0] (lcd pixel data output ports) vd[23:0] vd[23:0] vm (ac bias signal for lcd driver) vden (data enable signal) tp tp - lend (line end signal) sth sth lcd_pwren lcd_pwren lcd_pwren lcd_pwren -- lpc_oe lcc_inv -- lpc_rev lcc_rev -- lpc_revb lcc_revb
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-3 block diagram system bus lpc3600 is a timing control logic unit for lts350q1-pd1 or lts350q1-pd2. lcc3600 is a timing control logic unit for lts350q1-pe1 or lts350q1-pe2. regbank lcdcdma vidprcs lpc3600 timegen vd[23:0] vclk /lcd_hclk vline / hsync / cpv vframe / vsync / stv vm / vden / tp lcd_lpcoe / lcd_lccinv lcd_lpcrev / lcd_lccrev lcd_lpcrevb / lcd_lccrevb . . . video mux lcc3600 figure 15-1. lcd controller block diagram the S3C2440X lcd controller is used to transfer the video data and to generate the necessary control signals, such as vframe, vline, vclk, vm, and so on. in addition to the control signals, the S3C2440X has the data ports for video data, which are vd[23:0] as shown in figure 15-1. the lcd controller consists of a regbank, lcdcdma, vidprcs, timegen, and lpc3600 (see the figure 15-1 lcd controller block diagram). the regbank has 17 programmable register sets and 256x16 palette memory which are used to configure the lcd controller. the lcdcdma is a dedicated dma, which can transfer the video data in frame memory to lcd driver automatically. by using this special dma, the video data can be displayed on the screen without cpu intervention. the vidprcs receives the video data from the lcdcdma and sends the video data through the vd[23:0] data ports to the lcd driver after changing them into a suitable data format, for example 4/8-bit single scan or 4-bit dual scan display mode. the timegen consists of programmable logic to support the variable requirements of interface timing and rates commonly found in different lcd drivers. the timegen block generates vframe, vline, vclk, vm, and so on. the description of data flow is as follows: fifo memory is present in the lcdcdma. when fifo is empty or partially empty, the lcdcdma requests data fetching from the frame memory based on the burst memory transfer mode (consecutive memory fetching of 4 words (16 bytes) per one burst request without allowing the bus mastership to another bus master during the bus transfer). when the transfer request is accepted by bus arbitrator in the memory controller, there will be four successive word data transfers from system memory to internal fifo. the total size of fifo is 28 words, which consists of 12 words fifol and 16 words fifoh, respectively. the S3C2440X has two fifos to support the dual scan display mode. in case of single scan mode, one of the fifos (fifoh) can only be used.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-4 stn lcd controller operation timing generator (timegen) the timegen generates the control signals for the lcd driver, such as vframe, vline, vclk, and vm. these control signals are closely related to the configuration on the lcdcon1/2/3/4/5 registers in the regbank. based on these programmable configurations on the lcd control registers in the regbank, the timegen can generate the programmable control signals suitable to support many different types of lcd drivers. the vframe pulse is asserted for the duration of the entire first line at a frequency of once per frame. the vframe signal is asserted to bring the lcd's line pointer to the top of the display to start over. the vm signal helps the lcd driver alternate the polarity of the row and column voltages, which are used to turn the pixel on and off. the toggling rate of vm signals depends on the mmode bit of the lcdcon1 register and mval field of the lcdcon4 register. if the mmode bit is 0, the vm signal is configured to toggle on every frame. if the mmode bit is 1, the vm signal is configured to toggle on the every event of the elapse of the specified number of vline by the mval[7:0] value. figure 15-4 shows an example for mmode=0 and for mmode=1 with the value of mval[7:0]=0x2. when mmode=1, the vm rate is related to mval[7:0], as shown below: vm rate = vline rate / ( 2 x mval) the vframe and vline pulse generation relies on the configurations of the hozval field and the lineval field in the lcdcon2/3 register. each field is related to the lcd size and display mode. in other words, the hozval and lineval can be determined by the size of the lcd panel and the display mode according to the following equation: hozval = (horizontal display size / number of the valid vd data line)-1 in color mode: horizontal display size = 3 x number of horizontal pixel in the 4-bit single scan display mode, the number of valid vd data line should be 4. in case of 4-bit dual scan display, the number of valid vd data lineshould also be 4 while in case of 8-bit single scan display mode, the number of valid vd data line should be 8. lineval = (vertical display size) -1: in case of single scan display type lineval = (vertical display size / 2) -1: in case of dual scan display type the rate of vclk signal depends on the configuration of the clkval field in the lcdcon1 register. table 15-1 defines the relationship of vclk and clkval. the minimum value of clkval is 2. vclk(hz)=hclk/(clkval x 2) the frame rate is the vfram signal frequency. the frame rate is closely related to the field of wlh[1:0](vline pulse width) wdly[1:0] (the delay width of vclk after vline pulse), hozval, lineblank, and lineval in the lcdcon1/2/3/4 registers as well as vclk and hclk. most lcd drivers need their own adequate frame rate. the framerateiscalculatedasfollows: frame_rate(hz) = 1 / [ { (1/vclk) x (hozval+1)+(1/hclk) x ( a + b +(lineblank x 8) ) } x ( lineval+1) ] a =2 (4+wlh) , b =2 (4+wdly)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-5 table 15-1. relation between vclk and clkval (stn, hclk=60mhz) clkval 60mhz/x vclk 2 60 mhz/4 15.0 mhz 3 60 mhz/6 10.0 mhz ::: 1023 60 mhz/2046 29.3 khz video operation the S3C2440X lcd controller supports 8-bit color mode (256 color mode), 12-bit color mode (4096 color mode), 4 level gray scale mode, 16 level gray scale mode as well as the monochrome mode. for the gray or color mode, it is required to implement the shades of gray level or color according to time-based dithering algorithm and frame rate control (frc) method. the selection can be made following a programmable lockup table, which will be explained later. the monochrome mode bypasses these modules (frc and lookup table) and basically serializes the data in fifoh (and fifol if a dual scan display type is used) into 4-bit (or 8-bit if a 4-bit dual scan or 8-bit single scan display type is used) streams by shifting the video data to the lcd driver. the following sections describe the operation on the gray and color mode in terms of the lookup table and frc. lookup table the S3C2440X can support the lookup table for various selection of color or gray level mapping, ensuring flexible operation for users. the lookup table is the palette which allows the selection on the level of color or gray (selection on 4-gray levels among 16 gray levels in case of 4 gray mode, selection on 8 red levels among 16 levels, 8 green levels among 16 levels and 4 blue levels among 16 levels in case of 256 color mode). in other words, users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode. the gray levels cannot be selected in the 16 gray level mode; all 16 gray levels must be chosen among the possible 16 gray levels. in case of 256 color mode, 3 bits are allocated for red, 3 bits for green and 2 bits for blue. the 256 colors mean that the colors are formed from the combination of 8 red, 8 green and 4 blue levels (8x8x4 = 256). in the color mode, the lookup table can be used for suitable selections. eight red levels can be selected among 16 possible red levels, 8 green levels among 16 green levels, and 4 blue levels among 16 blue levels. in case of 4096 color mode, there is no selection as in the 256 color mode. gray mode operation the S3C2440X lcd controller supports two gray modes: 2-bit per pixel gray (4 level gray scale) and 4-bit per pixel gray (16 level gray scale). the 2-bit per pixel gray mode uses a lookup table (bluelut), which allows selection on 4 gray levels among 16 possible gray levels. the 2-bit per pixel gray lookup table uses the buleval[15:0] in blue lookup table (bluelut) register as same as blue lookup table in color mode. the gray level 0 will be denoted by blueval[3:0] value. if blueval[3:0] is 9, level 0 will be represented by gray level 9 among 16 gray levels. if blueval[3:0] is 15, level 0 will be represented by gray level 15 among 16 gray levels, and so on. following the same method as above, level 1 will also be denoted by blueval[7:4], the level 2 by blueval[11:8], and the level 3 by blueval[15:12]. these four groups among blueval[15:0] will represent level 0, level 1, level 2, and level 3. in 16 gray levels, there is no selection as in the 16 gray levels.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-6 256 level color mode operation the S3C2440X lcd controller can support an 8-bit per pixel 256 color display mode. the color display mode can generate 256 levels of color using the dithering algorithm and frc. the 8-bit per pixel are encoded into 3-bits for red, 3-bits for green, and 2-bits for blue. the color display mode uses separate lookup tables for red, green, and blue. each lookup table uses the redval[31:0] of redlut register, greenval[31:0] of greenlut register, and blueval[15:0] of bluelut register as the programmable lookup table entries. similar to the gray level display, 8 group or field of 4 bits in the redlur register, i.e., redval[31:28], redlut[27:24], redlut[23:20], redlut[19:16], redlut[15:12], redlut[11:8], redlut[7:4], and redlut[3:0], are assigned to each red level. the possible combination of 4 bits (each field) is 16, and each red level should be assigned to one level among possible 16 cases. in other words, the user can select the suitable red level by using this type of lookup table. for green color, the greenval[31:0] of the greenlut register is assigned as the lookup table, as was done in the case of red color. similarly, the blueval[15:0] of the bluelut register is also assigned as a lookup table. for blue color, 2 bits are allocated for 4 blue levels, different from the 8 red or green levels. 4096 level color mode operation the S3C2440X lcd controller can support a 12-bit per pixel 4096 color display mode. the color display mode can generate 4096 levels of color using the dithering algorithm and frc. the 12-bit per pixel are encoded into 4-bits for red, 4-bits for green, and 4-bits for blue. the 4096 color display mode does not use lookup tables.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-7 dithering and frame rate control for stn lcd displays (except monochrome), video data must be processed by a dithering algorithm. the dithfrc block has two functions, such as time-based dithering algorithm for reducing flicker and frame rate control (frc) for displaying gray and color level on the stn panel. the main principle of gray and color level display on the stn panel based on frc is described. for example, to display the third gray (3/16) level from a total of 16 levels, the 3 times pixel should be on and 13 times pixel off. in other words, 3 frames should be selected among the 16 frames, of which 3 frames should have a pixel-on on a specific pixel while the remaining 13 frames should have a pixel-off on a specific pixel. these 16 frames should be displayed periodically. this is basic principle on how to display the gray level on the screen, so-called gray level display by frc. the actual example is shown in table 15-2. to represent the 14 th gray level in the table, we should have a 6/7 duty cycle, which mean that there are 6 times pixel-on and one time pixel-off. the other cases for all gray levels are also shown in table 15-2. in the stn lcd display, we should be reminded of one item, i.e., flicker noise due to the simultaneous pixel-on and -off on adjacent frames. for example, if all pixels on first frame are turned on and all pixels on next frame are turned off, the flicker noise will be maximized. to reduce the flicker noise on the screen, the average probability of pixel-on and -off between frames should be the same. in order to realize this, the time-based dithering algorithm, which varies the pattern of adjacent pixels on every frame, should be used. this is explained in detail. for the 16 gray level, frc should have the following relationship between gray level and frc. the 15 th gray level should always have pixel-on, and the 14 th gray level should have 6 times pixel-on and one times pixel-off, and the 13 th gray level should have 4 times pixel-on and one times pixel-off, ,,,,,,,, , and the 0 th gray level should always have pixel-off as shown in table 15-2. table 15-2. dither duty cycle examples pre-dithered data (gray level number) duty cycle pre-dithered data (gray level number) duty cycle 15 1 7 1/2 14 6/7 6 3/7 13 4/5 5 2/5 12 3/4 4 1/3 11 5/7 3 1/4 10 2/3 2 1/5 93/511/7 84/70 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-8 display types the lcd controller supports 3 types of lcd drivers: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display mode. figure 15-2 shows these 3 different display types for monochrome displays, and figure 15-3 show these 3 different display types for color displays. 4-bit dual scan display type a 4-bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time. the 4 bits of data in the 8 parallel data lines are shifted to the upper half and 4 bits of data is shifted to the lower half, as shown in figure 15-2. the end of frame is reached when each half of the display has been shifted and transferred. the 8 pins (vd[7:0]) for the lcd output from the lcd controller can be directly connected to the lcd driver. 4-bit single scan display type a 4-bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. the 4 pins (vd[3:0]) for the lcd output from the lcd controller can be directly connected to the lcd driver, and the 4 pins (vd[7:4]) for the lcd output are not used. 8-bit single scan display type an 8-bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. the 8 pins (vd[7:0]) for the lcd output from the lcd controller can be directly connected to the lcd driver. 256 color displays color displays require 3 bits (red, green, and blue) of image data per pixel, and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line. resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line this rgb is shifted to the lcd driver as consecutive bits via the parallel data lines. figure 15-3 shows the rgb and order of the pixels in the parallel data lines for the 3 types of color displays. 4096 color displays color displays require 3 bits (red, green, and blue) of image data per pixel, and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line. this rgb is shifted to the lcd driver as consecutive bits via the parallel data lines. this rgb order is determined by the sequence of video data in video buffers.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-9 memory data format (stn, bswp=0) mono 4-bit dual scan display: video buffer memory: address data 0000h a[31:0] 0004h b[31:0] 1000h l[31:0] 1004h m[31:0] mono 4-bit single scan display & 8-bit single scan display: video buffer memory: address data 0000h a[31:0] 0004h b[31:0] 0008h c[31:0] lcd panel lcd panel a[31] a[30] ...... a[0] b[31] b[30] ...... b[0] ...... l[31] l[30] ...... l[0] m[31] m[30] ...... m[0] ...... a[31] a[30] a[29] ...... a[0] b[31] b[30] ...... b[0] c[31] ...... c[0] ......
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-10 memory data format ( stn, bswp=0 ) (continued) in 4-level gray mode, 2 bits of video data correspond to 1 pixel. in 16-level gray mode, 4 bits of video data correspond to 1 pixel. in 256 level color mode, 8 bits (3 bits of red, 3 bits of green, and 2 bits of blue) of video data correspond to 1 pixel. the color data format in a byte is as follows: bit [ 7:5 ] bit [ 4:2 ] bit[1:0] red green blue in 4096 level color mode, 12 bits (4 bits of red, 4 bits of green, 4 bits of blue) of video data correspond to 1 pixel. the following table shows color data format in words: (video data must reside at 3 word boundaries (8 pixel), as follows) rgb order data [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] word #1 red( 1) green(1) blue( 1) red( 2) green( 2) blue( 2) red(3) green(3) word #2 blue(3) red(4) green(4) blue(4) red(5) green(5) blue(5) red(6) word #3 green(6) blue(6) red(7) green(7) blue(7) red(8) green(8) blue(8)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-11 4-bit dual scan display 4-bit single scan display 8-bit single scan display ...... ...... vd3 vd2 vd1 vd0 vd3 vd2 vd1 vd0 vd3 vd2 vd1 vd0 vd3 vd2 vd1 vd0 vd3 vd2 vd1 vd0 vd3 vd2 vd1 vd0 ...... vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 ...... figure 15-2. monochrome display types (stn)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-12 vd3 r1 vd2 g1 vd1 b1 vd0 r2 vd3 g2 vd2 b2 vd1 r3 vd0 g3 . . . . . . 1pixel . . . . . . 4-bit dual scan display vd3 r1 vd2 g1 vd1 b1 vd0 r2 vd3 g2 vd2 b2 vd1 r3 vd0 g3 . . . . . . 1pixel 4-bit single scan display vd7 r1 vd6 g1 vd5 b1 vd4 r2 vd7 g2 vd6 b2 vd5 r3 vd4 g3 . . . . . . 1pixel 8-bit single scan display vd7 r1 vd6 g1 vd5 b1 vd4 r2 vd3 g2 vd2 b2 vd1 r3 vd0 g3 figure 15-3. color display types (stn)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-13 timing requirements image data should be transferred from the memory to the lcd driver using the vd[7:0] signal. vclk signal is used to clock the data into the lcd driver's shift register. after each horizontal line of data has been shifted into the lcd driver's shift register, the vline signal is asserted to display the line on the panel. the vm signal provides an ac signal for the display. the lcd uses the signal to alternate the polarity of the row and column voltages, which are used to turn the pixels on and off, because the lcd plasma tends to deteriorate whenever subjected to a dc voltage. it can be configured to toggle on every frame or to toggle every programmable number of vline signals. figure 15-4 shows the timing requirements for the lcd driver interface.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-14 wdly wlh line1line2line3line4line5line6 line1 linen first line timing linecnt decreases & display the 1st line lineblank first line check & data timing vframe vm vline vframe vm vline linecnt vclk vframe vm vline vclk vd[7:0] wdly wdly display the last line of the previous frame full frame timing(mmode = 1, mval=0x2) int_frsyn int_frsyn vframe vm vline full frame timing(mmode = 0) line1line2line3line4line5line6 line1 linen int_frsyn figure 15-4. 8-bit single scan display type stn lcd timing
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-15 tft lcd controller operation the timegen generates the control signals for lcd driver, such as vsync, hsync, vclk, vden, and lend signal. these control signals are highly related with the configurations on the lcdcon1/2/3/4/5 registers in the regbank. base on these programmable configurations on the lcd control registers in the regbank, the timegen can generate the programmable control signals suitable for the support of many different types of lcd drivers. the vsync signal is asserted to cause the lcd's line pointer to start over at the top of the display. the vsync and hsync pulse generation depends on the configurations of both the hozval field and the lineval field in the lcdcon2/3 registers. the hozval and lineval can be determined by the size of the lcd panel according to the following equations: hozval = (horizontal display size) -1 lineval = (vertical display size) -1 the rate of vclk signal depends on the clkval field in the lcdcon1 register. table 15-3 defines the relationship of vclk and clkval. the minimum value of clkval is 0. vclk(hz)=hclk/[(clkval+1)x2] the frame rate is vsync signal frequency. the frame rate is related with the field of vsync, vbpd, vfpd, lineval, hsync, hbpd, hfpd, hozval, and clkval in lcdcon1 and lcdcon2/3/4 registers. most lcd drivers need their own adequate frame rate. the frame rate is calculated as follows: frame rate = 1/ [ { (vspw+1) + (vbpd+1) + (liineval + 1) + (vfpd+1) } x {(hspw+1) + (hbpd +1) + (hfpd+1) + (hozval + 1) } x { 2 x ( clkval+1 ) / ( hclk ) } ] table 15-3. relation between vclk and clkval (tft, hclk=60mhz) clkval 60mhz/x vclk 1 60mhz/4 15.0mhz 2 60mhz/6 10.0mhz :: : 1023 60 mhz/2048 30.0 khz video operation the tft lcd controller within the S3C2440X supports 1, 2, 4 or 8 bpp (bit per pixel) palettized color displays and 16 or 24 bpp non-palettized true-color displays. 256 color palette the S3C2440X can support the 256 color palette for various selection of color mapping, providing flexible operation for users.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-16 memory data format (tft) this section includes some examples of each display mode. 24bpp display (bswp = 0, hwswp = 0, bpp24bl = 0) d[31:24] d[23:0] 000h dummy bit p1 004h dummy bit p2 008h dummy bit p3 ... (bswp = 0, hwswp = 0, bpp24bl = 1) d[31:8] d[7:0] 000h p1 dummy bit 004h p2 dummy bit 008h p3 dummy bit ... p1 p2 p3 p4 p5 ...... lcd panel vd pin descriptions at 24bpp vd 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 red 76543210 green 76543210 blue 76543210
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-17 16bpp display (bswp=0,hwswp=0) d[31:16] d[15:0] 000h p1 p2 004h p3 p4 008h p5 p6 ... (bswp=0,hwswp=1) d[31:16] d[15:0] 000h p2 p1 004h p4 p3 008h p6 p5 ... p1 p2 p3 p4 p5 ...... lcd panel vd pin descriptions at 16bpp (5:6:5) vd 23222120191817161514131211109876543210 red 43210 green 543210 blue nc nc 43210 nc (5:5:5:i) vd 23222120191817161514131211109876543210 red 43210 i green 43210 i blue nc nc 43210 i nc note : the unused vd pins can be used as gpio
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-18 8bpp display (bswp = 0, hwswp = 0) d[31:24] d[23:16] d[15:8] d[7:0] 000h p1 p2 p3 p4 004h p5 p6 p7 p8 008h p9 p10 p11 p12 ... (bswp = 1, hwswp = 0) d[31:24] d[23:16] d[15:8] d[7:0] 000h p4 p3 p2 p1 004h p8 p7 p6 p5 008h p12 p11 p10 p9 ... p1 p2 p3 p4 p5 ...... lcd panel p6 p7 p8 p10 p11 p12 p9
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-19 4bpp display (bswp=0,hwswp=0) d[31:28] d[27:24] d[23:20] d[19:16] d[15:12] d[11:8] d[7:4] d[3:0] 000h p1 p2 p3 p4 p5 p6 p7 p8 004h p9 p10 p11 p12 p13 p14 p15 p16 008h p17 p18 p19 p20 p21 p22 p23 p24 ... (bswp=1,hwswp=0) d[31:28] d[27:24] d[23:20] d[19:16] d[15:12] d[11:8] d[7:4] d[3:0] 000h p7 p8 p5 p6 p3 p4 p1 p2 004h p15 p16 p13 p14 p11 p12 p9 p10 008h p23 p24 p21 p22 p19 p20 p17 p18 ... 2bpp display (bswp=0,hwswp=0) d [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] 000h p1 p2 p3 p4 p5 p6 p7 p8 004h p17 p18 p19 p20 p21 p22 p23 p24 008h p33 p34 p35 p36 p37 p38 p39 p40 ... d [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 000h p9 p10 p11 p12 p13 p14 p15 p16 004h p25 p26 p27 p28 p29 p30 p31 p32 008h p41 p42 p43 p44 p45 p46 p47 p48 ...
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-20 256 palette usage (tft) palette configuration and format control the S3C2440X provides 256 color palette for tft lcd control. the user can select 256 colors from the 64k colors in these two formats. the 256 color palette consists of the 256 (depth) x 16-bit spsram. the palette supports 5:6:5 (r:g:b) format and 5:5:5:1(r:g:b:i) format. when the user uses 5:5:5:1 format, the intensity data(i) is used as a common lsb bit of each rgb data. so, 5:5:5:1 format is the same as r(5+i):g(5+i):b(5+i) format. in 5:5:5:1 format, for example, the user can write the palette as in table 15-5 and then connect vd pin to tft lcd panel(r(5+i)=vd[23:19]+vd[18], vd[10] or vd[2], g(5+i)=vd[15:11]+ vd[18], vd[10] or vd[2], b(5+i)=vd[7:3]+ vd[18], vd[10] or vd[2].), and set frm565 of lcdcon5 register to 0. table 15-4. 5:6:5 format index\bitpos.1514131211109876543210 address 00h r4r3r2r1r0g5g4g3g2g1g0b4 b3 b2 b1 b0 1) 0x4d000400 01h r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 0x4d000404 ....... ....... ffh r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 0x4d0007fc number of vd 232221201915141312111076543 table 15-5. 5:5:5:1 format index\bitpos.1514131211109876543210 address 00h r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 i 0x4d000400 01h r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 i 0x4d000404 ....... ....... ffh r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 i 0x4d0007fc number of vd 23 22 21 20 19 15 14 13 12 11 7 6 5 4 3 2) notes: 1. 0x4d000400 is palette start address. 2. vd18, vd10 and vd2 have the same output value, i. 3. data[31:16] is invalid. palette read/write when the user performs read/write operation on the palette, hstatus and vstatus of lcdcon5 register must be checked, for read/write operation is prohibited during the active status of hstatus and vstatus. temporary palette configuration the S3C2440X allows the user to fill a frame with one color without complex modification to fill the one color to the frame buffer or palette. the one colored frame can be displayed by the writing a value of the color which is displayed on lcd panel to tpalval of tpal register and enable tpalen.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-21 1 2 3 4 5 lcd panel 16bpp 5:5:5+1 format(non-palette) a[31] a[30] a[29] a[28] a[27] a[26]a[25] a[24] a[23] a[22] a[21] a[20] a[19]a[18] a[17] a[16] r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 r4 b3 b2 b1 b0 i a[15] a[14] a[13] a[12] a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 r4 b3 b2 b1 b0 i 1 2 3 4 5 lcd panel 16bpp 5:6:5 format(non-palette) a[31] a[30] a[29] a[28] a[27] a[26]a[25] a[24] a[23] a[22] a[21] a[20] a[19]a[18] a[17] a[16] a[15] a[14] a[13] a[12]a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 figure 15-5. 16bpp display types (tft)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-22 int_frsyn vsync hsync vden hsync vclk vd lend vbpd+1 vspw+1 vfpd+1 hbpd+1 hfpd+1 hspw+1 vden 1frame 1line lineval +1 hozval+1 figure 15-6. tft lcd timing example
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-23 samsung tft lcd panel (3.5? portrait / 256k color / reflective a-si/transflective a-si tft lcd) the S3C2440X supports following sec tft lcd panels. 1. samsung 3.5? portrait / 256k color /reflective a-si tft lcd. lts350q1-pd1: tft lcd panel with touch panel and front light unit lts350q1-pd2: tft lcd panel only 2. samsung 3.5? portrait / 256k color /transflective a-si tft lcd. lts350q1-pe1: tft lcd panel with touch panel and front light unit lts350q1-pe2: tft lcd panel only the S3C2440X provides timing signals as follows to use lts350q1-pd1 / pd2 and lts350q1-pe1 / pe2 lts350q1-pd1 / pd2 lts350q1-pe1 / pe2 sth: horizontal start pulse tp: source driver data load pulse inv: digital data inversion lcd_hclk: horizontal sampling clock cpv: vertical shift clock stv: vertical start pulse oe: gate on enable rev: inversion signal revb: inversion signal sth: horizontal start pulse tp:sourcedriverdataloadpulse inv: digital data inversion lcd_hclk: horizontal sampling clock cpv: vertical shift clock stv: vertical start pulse lccinv: source drive ic sampling inversion signal rev: vcom modulation signal revb: inversion signal so, lts350q1-pd1/2 and pe1/2 can be connected with the S3C2440X without using the additional timing control logic. but the user should additionally apply vcom generator circuit, various voltages, inv signal and gray scale voltage generator circuit, which is recommended by product information (spec) of lts350q1-pd1/2 and pe1/2. detailed timing diagram is also described in product information (spec) of lts350q1-pd1/2 and pe1/2. refer to the documentation (product information of lts350q1-pd1/2 and pe1/2), which is prepared by amlcd technical customer center of samsung electronics co., ltd. caution: the S3C2440X has hclk, working as the clock of ahb bus. accidentally, sec tft lcd panel (lts350q1-pd1/2 and pe1/2) has horizontal sampling clock (hclk). these two hclks may cause a confusion. so, note that hclk of the S3C2440X is hclk and other hclk of the lts350 is lcd_hclk. check that the hclk of sec tft lcd panel (lts350q1-pd1/2 and pe1/2) is changed to lcd_hclk.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-24 virtual display (tft/stn) the S3C2440X supports hardware horizontal or vertical scrolling. if the screen is scrolled, the fields of lcdbaseu and lcdbasel in lcdsaddr1/2 registers need to be changed (see figure 15-8), except the values of pagewidth and offsize. the video buffer in which the image is stored should be larger than the lcd panel screen in size. this is the data of line 1 of virtual screen. this is the data of line 1 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 11 of virtual screen. this is the data of line 11 of virtual screen. . . . before scrolling view port (the same size of lcd panel.) lineval + 1 offsize pagewidth this is the data of line 1 of virtual screen. this is the data of line 1 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 11 of virtual screen. this is the data of line 11 of virtual screen. . . . after scrolling lcdbaseu lcdbasel offsize figure 15-7. example of scrolling in virtual display (single scan)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-25 lcd power enable (stn/tft) the S3C2440X provides power enable (pwren) function. when pwren is set to make pwren signal enabled, the output value of lcd_pwren pin is controlled by envid. in other words, if lcd_pwren pin is connected to the power on/off control pin of the lcd panel, the power of lcd panel is controlled by the setting of envid automatically. the S3C2440X also supports invpwren bit to invert polarity of the pwren signal. this function is available only when lcd panel has its own power on/off control port and when port is connected to lcd_pwren pin. vsync hsync vden lcd_pwren 1frame envid lcd panel on tft lcd vline vframe stn lcd lcd_pwren lcd panel on envid figure 15-8. example of pwren function (pwren=1, invpwren=0)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-26 lcd controller special registers lcd control 1 register register address r/w description reset value lcdcon1 0x4d000000 r/w lcd control 1 register 0x00000000 lcdcon1 bit description initial state linecnt (read only) [27:18] provide the status of the line counter. down count from lineval to 0 0000000000 clkval [17:8] determine the rates of vclk and clkval[9:0]. stn : vclk = hclk / (clkval x 2) ( clkval 2) tft : vclk = hclk / [(clkval+1) x 2] ( clkval 0) 0000000000 mmode [7] determine the toggle rate of the vm. 0 = each frame 1 = the rate defined by the mval 0 pnrmode [6:5] select the display mode. 00 = 4-bit dual scan display mode (stn) 01 = 4-bit single scan display mode (stn) 10 = 8-bit single scan display mode (stn) 11 = tft lcd panel 00 bppmode [4:1] select the bpp (bits per pixel) mode. 0000 = 1 bpp for stn, monochrome mode 0001 = 2 bpp for stn, 4-level gray mode 0010 = 4 bpp for stn, 16-level gray mode 0011 = 8 bpp for stn, color mode 0100 = 12 bpp for stn, color mode 1000 = 1 bpp for tft 1001 = 2 bpp for tft 1010 = 4 bpp for tft 1011 = 8 bpp for tft 1100 = 16 bpp for tft 1101 = 24 bpp for tft 0000 envid [0] lcd video output and the logic enable/disable. 0 = disable the video output and the lcd control signal. 1 = enable the video output and the lcd control signal. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-27 lcd control 2 register register address r/w description reset value lcdcon2 0x4d000004 r/w lcd control 2 register 0x00000000 lcdcon2 bit description initial state vbpd [31:24] tft : vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. stn : these bits should be set to zero on stn lcd. 0x00 lineval [23:14] tft/stn : these bits determine the vertical size of lcd panel. 0000000000 vfpd [13:6] tft : vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. stn : these bits should be set to zero on stn lcd. 00000000 vspw [5:0] tft : vertical sync pulse width determines the vsync pulse's high level width by counting the number of inactive lines. stn : these bits should be set to zero on stn lcd. 000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-28 lcd control 3 register register address r/w description reset value lcdcon3 0x4d000008 r/w lcd control 3 register 0x00000000 lcdcon3 bit description initial state hbpd (tft) [25:19] tft : horizontal back porch is the number of vclk periods between the falling edge of hsync and the start of active data. 0000000 wdly (stn) stn : wdly[1:0] bits determine the delay between vline and vclk by counting the number of the hclk. wdly[7:2] are reserved. 00 = 16 hclk, 01 = 32 hclk, 10 = 48 hclk, 11 = 64 hclk hozval [18:8] tft/stn : these bits determine the horizontal size of lcd panel. hozval has to be determined to meet the condition that total bytes of 1 line are 4n bytes. if the x size of lcd is 120 dot in mono mode, x=120 cannot be supported because 1 line consists of 15 bytes. instead, x=128 in mono mode can be supported because 1 line is composed of 16 bytes (2n). lcd panel driver will discard the additional 8 dot. 00000000000 hfpd (tft) [7:0] tft : horizontal front porch is the number of vclk periods between the end of active data and the rising edge of hsync. 0x00 lineblank (stn) stn : these bits indicate the blank time in one horizontal line duration time. these bits adjust the rate of the vline finely. the unit of lineblank is hclk x 8. ex) if the value of lineblank is 10, the blank time is inserted to vclk during 80 hclk.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-29 lcd control 4 register register address r/w description reset value lcdcon4 0x4d00000c r/w lcd control 4 register 0x00000000 lcdcon4 bit description initial state mval [15:8] stn : these bit define the rate at which the vm signal will toggle if the mmode bit is set to logic '1'. 0x00 hspw(tft) [7:0] tft : horizontal sync pulse width determines the hsync pulse's high level width by counting the number of the vclk. 0x00 wlh(stn) stn : wlh[1:0] bits determine the vline pulse's high level width by counting the number of the hclk. wlh[7:2] are reserved. 00 = 16 hclk, 01 = 32 hclk, 10 = 48 hclk, 11 = 64 hclk
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-30 lcd control 5 register register address r/w description reset value lcdcon5 0x4d000010 r/w lcd control 5 register 0x00000000 lcdcon5 bit description initial state reserved [31:17] this bit is reserved and the value should be ?0?. 0 vstatus [16:15] tft : vertical status (read only). 00 = vsync 01 = back porch 10 = active 11 = front porch 00 hstatus [14:13] tft : horizontal status (read only). 00 = hsync 01 = back porch 10 = active 11 = front porch 00 bpp24bl [12] tft : this bit determines the order of 24 bpp video memory. 0 = lsb valid 1 = msb valid 0 frm565 [11] tft : this bit selects the format of 16 bpp output video data. 0 = 5:5:5:1 format 1 = 5:6:5 format 0 invvclk [10] stn/tft : this bit controls the polarity of the vclk active edge. 0 = the video data is fetched at vclk falling edge 1 = the video data is fetched at vclk rising edge 0 invvline [9] stn/tft : this bit indicates the vline/hsync pulse polarity. 0=normal 1=inverted 0 invvframe [8] stn/tft : this bit indicates the vframe/vsync pulse polarity. 0=normal 1=inverted 0 invvd [7] stn/tft : this bit indicates the vd (video data) pulse polarity. 0=normal 1=vdisinverted. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-31 lcd control 5 register (continued) lcdcon5 bit description initial state invvden [6] tft : this bit indicates the vden signal polarity. 0 = normal 1 = inverted 0 invpwren [5] stn/tft : this bit indicates the pwren signal polarity. 0 = normal 1 = inverted 0 invlend [4] tft : this bit indicates the lend signal polarity. 0 = normal 1 = inverted 0 pwren [3] stn/tft : lcd_pwren output signal enable/disable. 0 = disable pwren signal 1 = enable pwren signal 0 enlend [2] tft : lend output signal enable/disable. 0 = disable lend signal 1 = enable lend signal 0 bswp [1] stn/tft :byteswapcontrolbit. 0 = swap disable 1 = swap enable 0 hwswp [0] stn/tft : half-word swap control bit. 0 = swap disable 1 = swap enable 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-32 frame buffer start address 1 register register address r/w description reset value lcdsaddr1 0x4d000014 r/w stn/tft : frame buffer start address 1 register 0x00000000 lcdsaddr1 bit description initial state lcdbank [29:21] these bits indicate a[30:22] of the bank location for the video buffer in the system memory. lcdbank value cannot be changed even when moving the view port. lcd frame buffer should be within aligned 4mb region, which ensures that lcdbank value will not be changed when moving the view port. so, care should be taken to use the malloc() function. 0x00 lcdbaseu [20:0] for dual-scan lcd : these bits indicate a[21:1] of the start address of the upper address counter, which is for the upper frame memory of dual scan lcd or the frame memory of single scan lcd. for single-scan lcd : these bits indicate a[21:1] of the start address of the lcd frame buffer. 0x000000 frame buffer start address 2 register register address r/w description reset value lcdsaddr2 0x4d000018 r/w stn/tft : frame buffer start address 2 register 0x00000000 lcdsaddr2 bit description initial state lcdbasel [20:0] for dual-scan lcd: these bits indicate a[21:1] of the start address of the lower address counter, which is used for the lower frame memory of dual scan lcd. for single scan lcd: these bits indicate a[21:1] of the end address of the lcd frame buffer. lcdbasel = ((the frame end address) >>1) + 1 = lcdbaseu + (pagewidth+offsize) x (lineval+1) 0x0000 note: users can change the lcdbaseu and lcdbasel values for scrolling while the lcd controller is turned on. but, users must not change the value of the lcdbaseu and lcdbasel registers at the end of frame by referring to the linecnt field in lcdcon1 register, for the lcd fifo fetches the next frame data prior to the change in the frame. so, if you change the frame, the pre-fetched fifo data will be obsolete and lcd controller will display an incorrect screen. to check the linecnt, interrupts should be masked. if any interrupt is executed just after reading linecnt, the read linecnt value may be obsolete because of the execution time of interrupt service routine (isr).
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-33 frame buffer start address 3 register register address r/w description reset value lcdsaddr3 0x4d00001c r/w stn/tft : virtual screen address set 0x00000000 lcdsaddr3 bit description initial state offsize [21:11] virtual screen offset size (the number of half words). this value defines the difference between the address of the last half word displayed on the previous lcd line and the address of the first half word to be displayed in the new lcd line. 00000000000 pagewidth [10:0] virtual screen page width (the number of half words). this value defines the width of the view port in the frame. 000000000 note: the values of pagewidth and offsize must be changed when envid bit is 0. example 1. lcd panel = 320 x 240, 16gray, single scan frame start address = 0x0c500000 offset dot number = 2048 dots ( 512 half words ) lineval = 240-1 = 0xef pagewidth = 320 x 4 / 16 = 0x50 offsize = 512 = 0x200 lcdbank = 0x0c500000 >> 22 = 0x31 lcdbaseu = 0x100000 >> 1 = 0x80000 lcdbasel = 0x80000 + ( 0x50 + 0x200 ) x ( 0xef + 1 ) = 0xa2b00 example 2. lcd panel = 320 x 240, 16gray, dual scan frame start address = 0x0c500000 offset dot number = 2048 dots ( 512 half words ) lineval = 120-1 = 0x77 pagewidth = 320 x 4 / 16 = 0x50 offsize = 512 = 0x200 lcdbank = 0x0c500000 >> 22 = 0x31 lcdbaseu = 0x100000 >> 1 = 0x80000 lcdbasel = 0x80000 + ( 0x50 + 0x200 ) x ( 0x77 + 1 ) = 0x91580 example 3. lcd panel = 320*240, color, single scan frame start address = 0x0c500000 offset dot number = 1024 dots ( 512 half words ) lineval = 240-1 = 0xef pagewidth = 320 x 8 / 16 = 0xa0 offsize = 512 = 0x200 lcdbank = 0x0c500000 >> 22 = 0x31 lcdbaseu = 0x100000 >> 1 = 0x80000 lcdbasel = 0x80000 + ( 0xa0 + 0x200 ) x ( 0xef + 1 ) = 0xa7600
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-34 red lookup table register register address r/w description reset value redlut 0x4d000020 r/w stn : red lookup table register 0x00000000 redlut bit description initial state redval [31:0] these bits define which of the 16 shades will be chosen by each of the 8 possible red combinations. 000 = redval[3:0], 001 = redval[7:4] 010 = redval[11:8], 011 = redval[15:12] 100 = redval[19:16], 101 = redval[23:20] 110 = redval[27:24], 111 = redval[31:28] 0x00000000 green lookup table register register address r/w description reset value greenlut 0x4d000024 r/w stn : green lookup table register 0x00000000 greenlut bit description initial state greenval [31:0] these bits define which of the 16 shades will be chosen by each of the 8 possible green combinations. 000 = greenval[3:0], 001 = greenval[7:4] 010 = greenval[11:8], 011 = greenval[15:12] 100 = greenval[19:16], 101 = greenval[23:20] 110 = greenval[27:24], 111 = greenval[31:28] 0x00000000 blue lookup table register register address r/w description reset value bluelut 0x4d000028 r/w stn : blue lookup table register 0x0000 bulelut bit description initial state blueval [15:0] these bits define which of the 16 shades will be chosen by each of the 4 possible blue combinations. 00 = blueval[3:0], 01 = blueval[7:4] 10 = blueval[11:8], 11 = blueval[15:12] 0x0000 note: address from 0x14a0002c to 0x14a00048 should not be used. this area is reserved for test mode.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-35 dithering mode register register address r/w description reset value dithmode 0x4d00004c r/w stn : dithering mode register. this register reset value is 0x00000 but, user can change this value to 0x12210. (refer to a sample program source for the latest value of this register.) 0x00000 dithmode bit description initial state dithmode [18:0] use one of following value for your lcd : 0x00000 or 0x12210 0x00000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-36 temp palette register register address r/w description reset value tpal 0x4d000050 r/w tft : temporary palette register. this register value will be video data at next frame. 0x00000000 tpal bit description initial state tpalen [24] temporary palette register enable bit. 0 = disable 1 = enable 0 tpalval [23:0] temporary palette value register. tpalval[23:16] : red tpalval[15:8] : green tpalval[7:0] : blue 0x000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-37 lcd interrupt pending register register address r/w description reset value lcdintpnd 0x4d000054 r/w indicate the lcd interrupt pending register 0x0 lcdintpnd bit description initial state int_frsyn [1] lcd frame synchronized interrupt pending bit. 0 = the interrupt has not been requested. 1 = the frame has asserted the interrupt request. 0 int_ficnt [0] lcd fifo interrupt pending bit. 0 = the interrupt has not been requested. 1 = lcd fifo interrupt is requested when lcd fifo reaches trigger level. 0 lcd source pending register register address r/w description reset value lcdsrcpnd 0x4d000058 r/w indicate the lcd interrupt source pending register 0x0 lcdsrcpnd bit description initial state int_frsyn [1] lcd frame synchronized interrupt source pending bit. 0 = the interrupt has not been requested. 1 = the frame has asserted the interrupt request. 0 int_ficnt [0] lcd fifo interrupt source pending bit. 0 = the interrupt has not been requested. 1 = lcd fifo interrupt is requested when lcd fifo reaches trigger level. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-38 lcd interrupt mask register register address r/w description reset value lcdintmsk 0x4d00005c r/w determine which interrupt source is masked. the masked interrupt source will not be serviced. 0x3 lcdintmsk bit description initial state fiwsel [2] determine the trigger level of lcd fifo. 0 = 4 words 1 = 8 words int_frsyn [1] mask lcd frame synchronized interrupt. 0=theinterruptserviceisavailable. 1=theinterruptserviceismasked. 1 int_ficnt [0] mask lcd fifo interrupt. 0=theinterruptserviceisavailable. 1=theinterruptserviceismasked. 1
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-39 tcon control register register address r/w description reset value tconsel 0x4d000060 r/w this register controls the lpc3600/lcc3600 modes. 0xf84 tconsel bit description initial state lcc_test2 [11] lcc3600 test mode 2 ( read only ) 1 lcc_test1 [10] lcc3600 test mode 1 ( read only ) 1 lcc_sel5 [9] select stv polarity 1 lcc_sel4 [8] select cpv signal pin 0 1 lcc_sel3 [7] select cpv signal pin 1 1 lcc_sel2 [6] select line/dot inversion 0 lcc_sel1 [5] select dg/normal mode 0 lcc_en [4] determine lcc3600 enable/disable 0 = lcc3600 disable 1 = lcc3600 enable 0 cpv_sel [3] select cpv pulse low width 0 mode_sel [2] select de/sync mode 0 = sync mode 1 = de mode 1 res_sel [1] select output resolution type 0 = 320 x 240 1 = 240 x 320 0 lpc_en [0] determine lpc3600 enable/disable 0 = lpc3600 disable 1 = lpc3600 enable 0 note : both lpc_en and lcc_en enable is not permitted. only one tcon can be enabled at the same time.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-40 register setting guide (stn) the lcd controller supports multiple screen sizes by special register setting. the clkval value determines the frequency of vclk. this value has to be determined such that the vclk value is greater than data transmission rate. the data transmission rate for the vd port of the lcd controller is used to determine the value of clkval register. the data transmission rate is given by the following equation: data transmission rate = hs x vs x fr x mv hs: horizontal lcd size vs: vertical lcd size fr: frame rate mv: mode dependent value table 15-6. mv value for each display mode mode mv value mono, 4-bit single scan display 1/4 mono, 8-bit single scan display or 4-bit dual scan display 1/8 4 level gray, 4-bit single scan display 1/4 4 level gray, 8-bit single scan display or 4-bit dual scan display 1/8 16 level gray, 4-bit single scan display 1/4 16 level gray, 8-bit single scan display or 4-bit dual scan display 1/8 color, 4-bit single scan display 3/4 color, 8-bit single scan display or 4-bit dual scan display 3/8 the lcdbaseu register value is the first address value of the frame buffer. the lowest 4 bits must be eliminated for burst 4 word access. the lcdbasel register value depends on lcd size and lcdbaseu. the lcdbasel value is given by the following equation: lcdbasel = lcdbaseu + lcdbasel offset
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-41 example 1: 160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan display, hclk frequency is 60 mhz wlh = 1, wdly = 1. data transmission rate = 160 x 160 x 80 x 1/4 = 512 khz clkval = 58, vclk = 517khz hozval = 39, lineval = 159 lineblank =10 lcdbasel = lcdbaseu + 3200 note: the higher the system load is, the lower the cpu performance is. example 2 (virtual screen register): 4 -level gray, virtual screen size = 1024 x 1024, lcd size = 320 x 240, lcdbaseu = 0x64, 4-bit dual scan. 1 halfword = 8 pixels (4-level gray), virtual screen 1 line = 128 halfword = 1024 pixels, lcd 1 line = 320 pixels = 40 halfword, offsize = 128 - 40 = 88 = 0x58, pagewidth = 40 = 0x28 lcdbasel = lcdbaseu + (pagewidth + offsize) x (lineval +1) = 100 + (40 +88) x 120 = 0x3c64
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-42 gray level selection guide the S3C2440X lcd controller can generate 16 gray level using frame rate control (frc). the frc characteristics may cause unexpected patterns in gray level. these unwanted erroneous patterns may be shown in fast response lcd or at lower frame rates. because the quality of lcd gray levels depends on lcd's own characteristics, the user has to select an appropriate gray level after viewing all gray levels on user's own lcd. select the gray level quality through the following procedures: 1. get the latest dithering pattern register value from samsung. 2.display16graybarinlcd. 3. change the frame rate into an optimal value. 4. change the vm alternating period to get the best quality. 5. as viewing 16 gray bars, select a good gray level, which is displayed well on your lcd. 6. use only the good gray levels for quality. lcd refresh bus bandwidth calculation guide the S3C2440X lcd controller can support various lcd display sizes. to select a suitable size (for the flicker free lcd system application), the user have to consider the lcd refresh bus bandwidth determined by the lcd display size, bit per pixel (bpp), frame rate, memory bus width, memory type, and so on. lcd data rate (byte/s) = bpp x (horizontal display size) x (vertical display size) x (frame rate) /8 lcd dma burst count (times/s) = lcd data rate(byte/s) /16(byte) ; lcd dma using 4words(16byte) burst pdma means lcd dma access period. in other words, the value of pdma indicates the period of four-beat burst (4-words burst) for video data fetch. so, pdma depends on memory type and memory setting. eventually, lcd system load is determined by lcd dma burst count and pdma. lcd system load = lcd dma burst count x pdma example 3: 640 x 480, 8bpp, 60 frame/sec, 16-bit data bus width, sdram (trp=2hclk / trcd=2hclk / cl=2hclk) and hclk frequency is 60 mhz lcd data rate = 8 x 640 x 480 x 60 / 8 = 18.432mbyte/s lcd dma burst count = 18.432 / 16 = 1.152m/s pdma = (trp+trcd+cl+(2 x 4)+1) x (1/60mhz) = 0.250ms lcd system load = 1.152 x 250 = 0.288 system bus occupation rate = (0.288/1) x 100 = 28.8%
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor lcd controller 15-43 register setting guide (tft lcd) the clkval register value determines the frequency of vclk and frame rate. frame rate = 1/ [ { (vspw+1) + (vbpd+1) + (liineval + 1) + (vfpd+1) } x {(hspw+1) + (hbpd +1) + (hfpd+1) + (hozval + 1) } x { 2 x ( clkval+1 ) / ( hclk ) } ] for applications, the system timing must be considered to avoid under-run condition of the fifo of the lcd controller caused by memory bandwidth contention. example 4: tft resolution: 240 x 240, vspw =2, vbpd =14, lineval = 239, vfpd =4 hspw =25, hbpd =15, hozval = 239, hfpd =1 clkval = 5 hclk = 60 m (hz) the parameters below must be referenced by lcd size and driver specifications: vspw, vbpd, lineval, vfpd, hspw, hbpd, hozval, and hfpd if target frame rate is 60?70hz, then clkval should be 5. so, frame rate = 67hz
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. lcd controller S3C2440X risc microprocessor 15-44 notes
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor adc and touch screen interface 7-1 16 adc & touch screen interface overview the 10-bit cmos adc(analog to digital converter) is a recycling type device with 8-channel analog inputs. it converts the analog input signal into 10-bit binary digital codes at a maximum conversion rate of 500ksps with 2.5mhz a/d converter clock. a/d converter operates with on-chip sample-and-hold function and power down mode is supported. touch screen interface is controlling and selecting pads(xp, xm, yp, ym) of the touch screen for x, y position conversion. the touch screen interface contains touch screen pads control logic and adc interface logic with an interrupt generation logic. features ? resolution: 10-bit ? differential linearity error: 1.0 lsb ? integral linearity error: 2.0 lsb ? maximum conversion rate: 500 ksps ? low power consumption ? power supply voltage: 3.3v ? analog input range: 0 ~ 3.3v ? on-chip sample-and-hold function ? normal conversion mode ? separate x/y position conversion mode ? auto(sequential) x/y position conversion mode ? waiting for interrupt mode
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. adc and touch screen interface S3C2440X risc microprocessor 7-2 adc & touch screen interface operation block diagram figure 16-1 shows the functional block diagram of a/d converter and touch screen interface. note that the a/d converter device is a recycling type. pullup waiting for interrupt mode int_wk u int_adc 8:1 mux a/d converter adc input control touch screen pads control interrupt generation adc interface &touch screen control av d d agnd xp xm yp ym a[3:0] note note figure 16-1. adc and touch screen interface functional block diagram * note (symbol ) when touch screen device is used, xm or pm is only connected ground for touch screen i/f. when touch screen device is not used, xm or pm is connecting analog input signal for normal adc conversion.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor adc and touch screen interface 7-3 function descriptions a/d conversion time when the gclk frequency is 50mhz and the prescaler value is 49, total 10-bit conversion time is as follows. a/d converter freq. = 50mhz/(49+1) = 1mhz conversion time = 1/(1mhz / 5cycles) = 1/200khz = 5 us note: this a/d converter was designed to operate at maximum 2.5mhz clock, so the conversion rate can go up to 500 ksps. touch screen interface mode 1. normal conversion mode single conversion mode is the most likely used for general purpose adc conversion. this mode can be initialized by setting the adccon (adc control register) and completed with a read and a write to the adcdat0 (adc data register 0). 2. separate x/y position conversion mode touch screen controller can be operated by one of two conversion modes. separate x/y position conversion mode is operated as the following way. x-position mode writes x-position conversion data to adcdat0, so touch screen interface generates the interrupt source to interrupt controller. y-position mode writes y-position conversion data to adcdat1, so touch screen interface generates the interrupt source to interrupt controller. 3. auto(sequential) x/y position conversion mode auto(sequential) x/y position conversion mode is operated as the following. touch screen controller sequentially converts x-position and y-position that is touched. after touch controller writes x-measurement data to adcdat0 and writes y-measurement data to adcdat1, touch screen interface is generating interrupt source to interrupt controller in auto position conversion mode. 4. waiting for interrupt mode touch screen controller is generating wake-up (wku) signal when the system is stop mode (power down). the waiting for interrupt mode of touch screen controller must be set state of pads(xp, xm, yp, ym) in touch screen interface. after touch screen controller is generating wake-up signal (int_wku), waiting for interrupt mode must be cleared. (xy_pst sets to the no operation mode) standby mode standby mode is activated when adccon [2] is set to '1'. in this mode, a/d conversion operation is halted and adcdat0, adcdat1 register contains the previous converted data.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. adc and touch screen interface S3C2440X risc microprocessor 7-4 programming notes 1. the a/d converted data can be accessed by means of interrupt or polling method. with interrupt method the overall conversion time - from a/d converter start to converted data read - may be delayed because of the return time of interrupt service routine and data access time. with polling method, by checking the adccon[15] - end of conversion flag-bit, the read time from adcdat register can be determined. 2. another way for starting a/d conversion is provided. after adccon[1] - a/d conversion start-by-read mode-is set to 1, a/d conversion starts simultaneously whenever converted data is read. xp x-tal clk is used x-conversion yp gclk is used y-conversion pen touch figure 16-2 adc and touch screen operation signal
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor adc and touch screen interface 7-5 adc and touch screen interface special registers adc control register (adccon) register address r/w description reset value adccon 0x5800000 r/w adc control register 0x3fc4 adccon bit description initial state ecflg [15] end of conversion flag(read only) 0=a/dconversioninprocess 1 = end of a/d conversion 0 prscen [14] a/d converter prescaler enable 0 = disable 1 = enable 0 prscvl [13:6] a/d converter prescaler value data value: 0 ~ 255 note that division factor is (n+1) when prescaler value is n. 0xff sel_mux [5:3] analog input channel select 000 = ain 0 001 = ain 1 010 = ain 2 011 = ain 3 100 = ym 101 = yp 110 = xm 111 = xp 0 stdbm [2] standby mode select 0 = normal operation mode 1 = standby mode 1 read_ start [1] a/d conversion start by read 0 = disable start by read operation 1 = enable start by read operation 0 enable_start [0] a/d conversion starts by enable. if read_start is enabled, this value is not valid. 0 = no operation 1 = a/d conversion starts and this bit is cleared after the start-up. 0 note : when touch screen pads(ym, yp, xm, xp) were disabled, these ports can be used as analog input ports(ain4, ain5, ain6, ain7) for adc.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. adc and touch screen interface S3C2440X risc microprocessor 7-6 adc touch screen control register (adctsc) register address r/w description reset value adctsc 0x5800004 r/w adc touch screen control register 0x58 adctsc bit description initial state ud_sen [8] detect stylus up or down status. 0 = detect stylus down interrupt signal. 1 = detect stylus up interrupt signal. 0 ym_sen [7] ym switch enable 0 = ym output driver disable. 1 = ym output driver enable. 0 yp_sen [6] yp switch enable 0 = yp output driver enable. 1 = yp output driver disable. 1 xm_sen [5] xm switch enable 0 = xm output driver disable. 1 = xm output driver enable. 0 xp_sen [4] xp switch enable 0 = xp output driver enable. 1 = xp output driver disable. 1 pull_up [3] pull-up switch enable 0 = xp pull-up enable. 1 = xp pull-up disable. 1 auto_pst [2] automatically sequencing conversion of x-position and y-position 0 = normal adc conversion. 1 = auto sequential measurement of x-position, y-position. 0 xy_pst [1:0] manually measurement of x-position or y-position. 00 = no operation mode 01 = x-position measurement 10 = y-position measurement 11 = waiting for interrupt mode 0 note: 1) while waiting for touch screen interrupt, xp_sen bit should be set to ? 1 ?, namely ?xp output disable? and pull_up bit should be set to ?0?, namely ?xp pull-up enable?. 2) auto_pst bit should be set ?1? only in automatic & sequential x/y position conversion. touch screen pin conditions in x/y position conversion. xp xm yp ym adc ch. select x position vref gnd hi-z hi-z yp y position hi-z hi-z vref gnd xp
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor adc and touch screen interface 7-7 adc start delay register (adcdly) register address r/w description reset value adcdly 0x5800008 r/w adc start or interval delay register 0x00ff adcdly bit description initial state delay [15:0] 1) normal conversion mode, xy position mode, auto position mode. adc conversion start delay value. 2) waiting for interrupt mode. when stylus down occurs at sleep mode, generates wake-up signal, having interval(several ms), for exiting sleep mode. note) don?t use zero value(0x0000) 00ff note: before adc conversion, touch screen uses x-tal clock(3.68mhz). during adc conversion gclk( max. 50mhz) is used.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. adc and touch screen interface S3C2440X risc microprocessor 7-8 adc conversion data register (adcdat0) register address r/w description reset value adcdat0 0x580000c r adc conversion data register - adcdat0 bit description initial state updown [15] up or down state of stylus at waiting for interrupt mode. 0=stylusdownstate. 1 = stylus up state. - auto_pst [14] automatic sequencing conversion of x-position and y-position 0 = normal adc conversion. 1 = sequencing measurement of x-position, y-position. - xy_pst [13:12] manually measurement of x-position or y-position. 00 = no operation mode 01 = x-position measurement 10 = y-position measurement 11 = waiting for interrupt mode - reserved [11:10] reserved xpdata (normal adc) [9:0] x-position conversion data value (include normal adc conversion data value) datavalue: 0~3ff -
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor adc and touch screen interface 7-9 adc conversion data register (adcdat1) register address r/w description reset value adcdat1 0x5800010 r adc conversion data register - adcdat1 bit description initial state updown [15] up or down state of stylus at waiting for interrupt mode. 0 = stylus down state. 1 = no stylus down state. - auto_pst [14] automatically sequencing conversion of x-position and y-position 0 = normal adc conversion. 1 = sequencing measurement of x-position, y-position. - xy_pst [13:12] manually measurement of x-position or y-position. 00 = no operation mode 01 = x-position measurement 10 = y-position measurement 11 = waiting for interrupt mode - reserved [11:10] reserved ypdata [9:0] y-position conversion data value datavalue: 0~3ff -
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. adc and touch screen interface S3C2440X risc microprocessor 7-10 adc touch screen up-down register (adcupdn) register address r/w description reset value adcupdn 0x5800014 r/w stylus up or down interrpt status register 0x0 adcupdn bit description initial state tsc_up [1] stylus up interrupt. 0 = no stylus up status. 1 = stylus up status. 0 tsc_dn [0] stylus down interrupt. 0 = no stylus down status. 1=stylusdownstatus. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor real time clock 17-1 17 real time clock overview the real time clock (rtc) unit can be operated by the backup battery while the system power is off. the rtc can transmit 8-bit data to cpu as binary coded decimal (bcd) values using the strb/ldrb arm operation. the data include the time by second, minute, hour, date, day, month, and year. the rtc unit works with an external 32.768 khz crystal and also can perform the alarm function. features ? bcd number: second, minute, hour, date, day, month, and year ? leap year generator ? alarm function: alarm interrupt or wake-up from power-off mode ? year 2000 problem is removed. ? independent power pin (rtcvdd) ? supports millisecond tick time interrupt for rtos kernel time tick. ? round reset function
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. real time clock S3C2440X risc microprocessor 17-2 real time clock operation 2 15 clock divider xtortc xtirtc control register sec min hour day date mon year leap year generator alarm generator reset register 1hz almint rtccon rtcalm rtcrst time tick generator time tick ticnt 128 hz pmwkup pwdn figure 17-1. real time clock block diagram leap year generator the leap year generator can determine the last date of each month out of 28, 29, 30, or 31, based on data from bcddate, bcdmon, and bcdyear. this block considers leap year in deciding on the last date. an 8-bit counter can only represent 2 bcd digits, so it cannot decide whether "00" year (the year with its last two digits zeros) is a leap year or not. for example, it cannot discriminate between 1900 and 2000. to solve this problem, the rtc block in S3C2440X has hard-wired logic to support the leap year in 2000. note 1900 is not leap year while 2000 is leap year. therefore, two digits of 00 in S3C2440X denote 2000, not 1900. read/write registers bit 0 of the rtccon register must be set high in order to write the bcd register in rtc block. to display the second, minute, hour, date, month, and year, the cpu should read the data in bcdsec, bcdmin, bcdhour, bcdday, bcddate, bcdmon, and bcdyear registers, respectively, in the rtc block. however, a one second deviation may exist because multiple registers are read. for example, when the user reads the registers from bcdyear to bcdmin, the result is assumed to be 2059 (year), 12 (month), 31 (date), 23 (hour) and 59 (minute). when the user read the bcdsec register and the value ranges from 1 to 59 (second), there is no problem, but, if the value is 0 sec., the year, month, date, hour, and minute may be changed to 2060 (year), 1 (month), 1 (date), 0 (hour) and 0 (minute) because of the one second deviation that was mentioned. in this case, the user should re- read from bcdyear to bcdsec if bcdsec is zero. backup battery operation the rtc logic can be driven by the backup battery, which supplies the power through the rtcvdd pin into the rtc block, even if the system power is off. when the system is off, the interfaces of the cpu and rtc logic should be blocked, and the backup battery only drives the oscillation circuit and the bcd counters to minimize power dissipation.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor real time clock 17-3 alarm function the rtc generates an alarm signal at a specified time in the power-off mode or normal operation mode. in normal operation mode, the alarm interrupt (almint) is activated. in the power-off mode, the power management wakeup (pmwkup) signal is activated as well as the almint. the rtc alarm register (rtcalm) determines the alarm enable/disable status and the condition of the alarm time setting. tick time interrupt the rtc tick time is used for interrupt request. the ticnt register has an interrupt enable bit and the count value for the interrupt. the count value reaches '0' when the tick time interrupt occurs. then the period of interrupt is as follows: period = ( n+1 ) / 128 second n: tick time count value (1~127) this rtc time tick may be used for real time operating system (rtos) kernel time tick. if time tick is generated by the rtc time tick, the time related function of rtos will always synchronized in real time. round reset function the round reset function can be performed by the rtc round reset register (rtcrst). the round boundary (30, 40, or 50 sec.) of the second carry generation can be selected, and the second value is rounded to zero in the round reset. for example, when the current time is 23:37:47 and the round boundary is selected to 40 sec, the round reset changes the current time to 23:38:00. note all rtc registers have to be accessed for each byte unit using the strb and ldrb instructions or char type pointer. 32.768khz x-tal connection example the figure 17-2 shows a circuit of the rtc unit oscillation at 32.768khz. xtirtc xtortc 32768hz 15~ 22pf figure 17-2. main oscillator circuit example
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. real time clock S3C2440X risc microprocessor 17-4 real time clock special registers real time clock control (rtccon) register the rtccon register consists of 4 bits such as the rtcen, which controls the read/write enable of the bcd registers, clksel, cntsel, and clkrst for testing. rtcen bit can control all interfaces between the cpu and the rtc, so it should be set to 1 in an rtc control routine to enable data read/write after a system reset. also before power off, the rtcen bit should be cleared to 0 to prevent inadvertent writing into rtc registers. register address r/w description reset value rtccon 0x57000040(l) 0x57000043(b) r/w (by byte) rtc control register 0x0 rtccon bit description initial state clkrst [3] rtc clock count reset. 0=noreset, 1=reset 0 cntsel [2] bcd count select. 0=mergebcdcounters 1 = reserved (separate bcd counters) 0 clksel [1] bcd clock select. 0 = xtal 1/2 15 divided clock 1 = reserved (xtal clock only for test) 0 rtcen [0] rtc control enable. 0 = disable 1 = enable note: only bcd time count and read operation can be performed. 0 notes: 1. all rtc registers have to be accessed for each byte unit using strb and ldrb instructions or char type pointer. 2. (l): little endian. (b): big endian. tick time count (ticnt) register register address r/w description reset value ticnt 0x57000044(l) 0x57000047(b) r/w (by byte) tick time count register 0x0 ticnt bit description initial state tick int enable [7] tick time interrupt enable. 0 = disable 1 = enable 0 tick time count [6:0] tick time count value (1~127). this counter value decreases internally, and users cannot read this counter value in working. 000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor real time clock 17-5 rtc alarm control (rtcalm) register the rtcalm register determines the alarm enable and the alarm time. note that the rtcalm register generates the alarm signal through both almint and pmwkup in power down mode, but only through almint in the normal operation mode. register address r/w description reset value rtcalm 0x57000050(l) 0x57000053(b) r/w (by byte) rtc alarm control register 0x0 rtcalm bit description initial state reserved [7] 0 almen [6] alarm global enable. 0 = disable, 1 = enable 0 yearen [5] year alarm enable. 0 = disable, 1 = enable 0 monren [4] month alarm enable. 0 = disable, 1 = enable 0 dateen [3] date alarm enable. 0 = disable, 1 = enable 0 houren [2] hour alarm enable. 0 = disable, 1 = enable 0 minen [1] minute alarm enable. 0 = disable, 1 = enable 0 secen [0] second alarm enable. 0 = disable, 1 = enable 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. real time clock S3C2440X risc microprocessor 17-6 alarm second data (almsec) register register address r/w description reset value almsec 0x57000054(l) 0x57000057(b) r/w (by byte) alarm second data register 0x0 almsec bit description initial state reserved [7] 0 secdata [6:4] bcd value for alarm second. 0~5 000 [3:0] 0 ~ 9 0000 alarm min data (almmin) register register address r/w description reset value almmin 0x57000058(l) 0x5700005b(b) r/w (by byte) alarm minute data register 0x00 almmin bit description initial state reserved [7] 0 mindata [6:4] bcd value for alarm minute. 0~5 000 [3:0] 0 ~ 9 0000 alarm hour data (almhour) register register address r/w description reset value almhour 0x5700005c(l) 0x5700005f(b) r/w (by byte) alarm hour data register 0x0 almhour bit description initial state reserved [7:6] 00 hourdata [5:4] bcd value for alarm hour. 0~2 00 [3:0] 0 ~ 9 0000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor real time clock 17-7 alarm date data (almdate) register register address r/w description reset value almdate 0x57000060(l) 0x57000063(b) r/w (by byte) alarm date data register 0x01 almdate bit description initial state reserved [7:6] 00 datedata [5:4] bcd value for alarm date, from 0 to 28, 29, 30, 31. 0~3 00 [3:0] 0 ~ 9 0001 alarm mon data (almmon) register register address r/w description reset value almmon 0x57000064(l) 0x57000067(b) r/w (by byte) alarm month data register 0x01 almmon bit description initial state reserved [7:5] 00 mondata [4] bcd value for alarm month. 0~1 0 [3:0] 0 ~ 9 0001 alarm year data (almyear) register register address r/w description reset value almyear 0x57000068(l) 0x5700006b(b) r/w (by byte) alarm year data register 0x0 almyear bit description initial state yeardata [7:0] bcd value for year. 00 ~ 99 0x0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. real time clock S3C2440X risc microprocessor 17-8 rtc round reset (rtcrst) register register address r/w description reset value rtcrst 0x5700006c(l) 0x5700006f(b) r/w (by byte) rtc round reset register 0x0 rtcrst bit description initial state srsten [3] round second reset enable. 0 = disable, 1 = enable 0 seccr [2:0] round boundary for second carry generation. 011 = over than 30 sec 100 = over than 40 sec 101 = over than 50 sec note: if other values (0, 1, 2, 6, or 7) are set, no second carry is generated. but second value can be reset. 000 bcd second (bcdsec) register register address r/w description reset value bcdsec 0x57000070(l) 0x57000073(b) r/w (by byte) bcd second register undefined bcdsec bit description initial state secdata [6:4] bcd value for second. 0~5 - [3:0] 0 ~ 9 - bcd minute (bcdmin) register register address r/w description reset value bcdmin 0x57000074(l) 0x57000077(b) r/w (by byte) bcd minute register undefined bcdmin bit description initial state mindata [6:4] bcd value for minute. 0~5 - [3:0] 0 ~ 9 -
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor real time clock 17-9 bcd hour (bcdhour) register register address r/w description reset value bcdhour 0x57000078(l) 0x5700007b(b) r/w (by byte) bcd hour register undefined bcdhour bit description initial state reserved [7:6] - hourdata [5:4] bcd value for hour. 0~2 - [3:0] 0 ~ 9 - bcd date (bcddate) register register address r/w description reset value bcddate 0x5700007c(l) 0x5700007f(b) r/w (by byte) bcd date register undefined bcddate bit description initial state reserved [7:6] - datedata [5:4] bcd value for date. 0~3 - [3:0] 0 ~ 9 - bcd day (bcdday) register register address r/w description reset value bcdday 0x57000080(l) 0x57000083(b) r/w (by byte) bcd a day of the week register undefined bcdday bit description initial state reserved [7:3] - daydata [2:0] bcd value for a day of the week. 1~7 -
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. real time clock S3C2440X risc microprocessor 17-10 bcd month (bcdmon) register register address r/w description reset value bcdmon 0x57000084(l) 0x57000087(b) r/w (by byte) bcd month register undefined bcdmon bit description initial state reserved [7:5] - mondata [4] bcd value for month. 0~1 - [3:0] 0 ~ 9 - bcd year (bcdyear) register register address r/w description reset value bcdyear 0x57000088(l) 0x5700008b(b) r/w (by byte) bcd year register undefined bcdyear bit description initial state yeardata [7:0] bcd value for year. 00 ~ 99 -
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor w a tch-dog timer 18-1 watchdog timer overview the S3C2440X watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. it can be used as a normal 16-bit interval timer to request interrupt service. the watchdog timer generates the reset signal for 128 pclk cycles. features ? normal interval timer mode with interrupt request ? internal reset signal is activated for 128 pclk cycles when the timer count value reaches 0 (time-out).
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. w a tchdog timer s3c2440 x risc microprocessor 18-2 watchdog timer operation figure 18-1 shows the functional block diagram of the watchdog timer. the watchdog timer uses only pclk as its source clock. the pclk frequency is prescaled to generate the corresponding watchdog timer clock, and the resulting frequency is divided again. reset signal generator wtcnt (down counter) pclk wtcon[4:3] wtdat reset 1/16 1/32 1/64 1/128 8-bit prescaler wtcon[15:8] wtcon[2] wtcon[0] interrupt mux figure 18-1. watchdog timer block diagram the prescaler value and the frequency division factor are specified in the watchdog timer control (wtcon) register. valid prescaler values range from 0 to 2 8 -1. the frequency division factor can be selected as 16, 32, 64, or 128. use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle: t_watchdog = 1/[ pclk / (prescaler value + 1) / division_factor ] wtdat & wtcnt once the watchdog timer is enabled, the value of watchdog timer data (wtdat) register cannot be automatically reloaded into the timer counter (wtcnt). in this reason, an initial value must be written to the watchdog timer count (wtcnt) register, before the watchdog timer starts. consideration of debugging environment when the S3C2440X is in debug mode using embedded ice, the watchdog timer must not operate. the watchdog timer can determine whether or not it is currently in the debug mode from the cpu core signal (dbgack signal). once the dbgack signal is asserted, the reset output of the watchdog timer is not activated as the watchdog timer is expired.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor w a tch-dog timer 18-3 watchdog timer special registers watchdog timer control (wtcon) register the wtcon register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. the watchdog timer is used to resume the S3C2440X restart on mal-function after its power on; if controller restart is not desired, the watchdog timer should be disabled. if the user wants to use the normal timer provided by the watchdog timer, enable the interrupt and disable the watchdog timer. register address r/w description reset value wtcon 0x53000000 r/w watchdog timer control register 0x8021 wtcon bit description initial state prescaler value [15:8] prescaler value. the valid range is from 0 to 255(2 8 -1). 0x80 reserved [7:6] reserved. these two bits must be 00 in normal operation. 00 watchdog timer [5] enable or disable bit of watchdog timer. 0=disable 1 = enable 1 clock select [4:3] determine the clock division factor. 00: 16 01 : 32 10: 64 11 : 128 00 interrupt generation [2] enable or disable bit of the interrupt. 0=disable 1 = enable 0 reserved [1] reserved. this bit must be 0 in normal operation. 0 reset enable/disable [0] enable or disable bit of watchdog timer output for reset signal. 1: assert reset signal of the S3C2440X at watchdog time- out 0: disable the reset function of the watchdog timer. 1
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. w a tchdog timer s3c2440 x risc microprocessor 18-4 watchdog timer data (wtdat) register the wtdat register is used to specify the time-out duration. the content of wtdat cannot be automatically loaded into the timer counter at initial watchdog timer operation. however, using 0x8000 (initial value) will drive the first time-out. in this case, the value of wtdat will be automatically reloaded into wtcnt. register address r/w description reset value wtdat 0x53000004 r/w watchdog timer data register 0x8000 wtdat bit description initial state count reload value [15:0] watchdog timer count value for reload. 0x8000 watchdog timer count (wtcnt) register the wtcnt register contains the current count values for the watchdog timer during normal operation. note that the content of the wtdat register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially, so the wtcnt register must be set to an initial value before enabling it. register address r/w description reset value wtcnt 0x53000008 r/w watchdog timer count register 0x8000 wtcnt bit description initial state count value [15:0] the current count value of the watchdog timer 0x8000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor sdi 19-1 sdi overview the S3C2440X sdi(secure digital interface) can interface for sd memory card, sdio device and mmc(multi- media card). features ? sd memory card spec(ver 1.0) / mmc spec(2.11) compatible ? sdio card spec(ver 1.0) compatible ? 16 words(64 bytes) fifo(depth 16) for data tx/rx ? 40-bit command register ? 136-bit response register ? 8-bit prescaler logic(freq = system clock / (p + 1)) ? crc7 & crc16 generator ? normal, and dma data transfer mode(byte or word transfer) ? 1bit / 4bit(wide bus) mode & block / stream mode switch support
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. sdi S3C2440X risc microprocessor 19-2 block diagram cmd reg (5byte) resp reg (17byte) cmd control 8bit shift reg crc7 prescaler fifo (64byte) dat control 32bit shift reg crc16*4 dma int apb i/f 32 32 8 8 32 32 32 32 32 32 paddr psel pclk pwdata [31:0] prdata [31:0] dreq dack int txcmd rxcmd sdclk txdat[3:0] rxdat[3:0]
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X microprocessor sdi 19-3 sd operation a serial clock line synchronizes shifting and sampling of the information on the five data lines. the transmission frequency is controlled by making the appropriate bit settings to the sdipre register. you can modify its frequency to adjust the baud rate data register value. programming procedure (common) to program the sdi modules, follow these basic steps : 1. set sdicon to configure properly with clock & interrupt enable 2. set sdipre to configure with a proper value. 3. wait 74 sdclk clock cycle in order to initialize the card. cmd path programming 1. write command argument 32bit to sdicarg. 2. determine command types and start command transmit with setting sdiccon. 3. confirm the end of sdi cmd path operation when the specific flag of sdicsta is set 4. the flag is cmdsent if command type is no response. 5. the flag is rspfin if command type is with response. 6. clear the corresponding flag of sdicsta through writing one with this bit dat path programming 1. write data timeout period to sdidtimer. 2. write block size(block length) to sdibsize(normally 0x80 word). 3. determine the mode of block, wide bus, dma, etc and start data transfer with setting sdidcon. 4. tx data write data to data register(sdidat) while tx fifo is available(tfdet is set), or half(tfhalf is set), or empty(tfempty is set). 5. rx data read data from data register(sdidat) while rx fifo is available(rfdet is set), or full(rffull is set), or half(rfhalf is set), or ready for last data(rflast is set). 6. confirm the end of sdi dat path operation when datfin flag of sdidsta is set 7. clear the corresponding flag of sdidsta through writing one with this bit
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. sdi S3C2440X risc microprocessor 19-4 sdio operation there are two functions of sdio operation: sdio interrupt receiving and read wait request generation. these two functions can operate when rcvioint bit and rwaiten bit of sdicon register is activated respectively. and two functions have the steps and conditions below:- sdio interrupt in sd 1bit mode, interrupt is received through all range from rxdat[1] pin. in sd 4bit mode, rxdat[1] pin is shared between data receiving and interrupt receiving. when interrupt detection range(interrupt period) is : 1. single block : the time between a and b - a : 2clocks after the completion of a data packet - b : the completion of sending the end bit of the next with data command 2. multi block, prdtype = 0 : the time between a and b, restart at c - a : 2clocks after the completion of a data packet - b : 2clocks after a - c : 2clocks after the end bit of the abort command response 3. multi block, prdtype = 1 : the time between a and b, restart at a - a : 2clocks after the completion of a data packet - b : 2clocks after a - in case of last block, interrupt period begins at a, but not ends at b(cmd53 case) read wait request regardless of 1bit or 4bit mode, read wait request signal transmits to txdat[2] pin in condition of below. - in read multiple operation, request signal transmission begins at 2clocks after the end of the data block - transmission ends when user sets to one rwaitreq bit of sdidsta register
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X microprocessor sdi 19-5 sdi special registers sdi control register(sdicon) register address r/w description reset value sdicon 0x5a000000 r/w sdi control register 0x0 sdicon bit description initial value reserved [31:6] clock type (ctyp) [5] determines which clock type is used as sdclk. 0 = sd type, 1 = mmc type 0 byte order type(byteorder) [4] determines byte order type when you read(write) data from(to) sd host fifo with word boundary. 0=typea, 1=typeb 0 receive sdio interrupt from card (rcvioint) [3] determines whether sd host receives sdio interrupt from the card or not(for sdio). 0 = ignore, 1 = receive sdio interrupt 0 read wait enable(rwaiten) [2] determines read wait request signal generate when sd host waits the next block in multiple block read mode. this bit needs to delay the next block to be transmitted from the card(for sdio). 0 = disable(no generate), 1 = read wait enable(use sdio) 0 fifo reset(frst) [1] reset fifo value. this bit is automatically clear. 0 = normal mode, 1 = fifo reset 0 clock out enable (enclk) [0] determines whether sdclk out enable or not 0 = disable(prescaler off), 1 = clock enable 0 * byte order type - type a : d[7:0] d[15:8] d[23:16] d[31:24] - type b : d[31:24] d[23:16] d[15:8] d[7:0] sdi baud rate prescaler register(sdipre) register address r/w description reset value sdipre 0x5a000004 r/w sdi buad rate prescaler register 0x01 sdipre bit description initial value prescaler value [7:0] determines sdi clock (sdclk) rate as above equation. baud rate = pclk / (prescaler value + 1) 0x01 * prescaler value should be greater than zero. sdi command argument register (sdicarg) register address r/w description reset value sdicarg 0x5a000008 r/w sdi command argument register 0x0 sdicarg bit description initial value cmdarg [31:0] command argument 0x00000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. sdi S3C2440X risc microprocessor 19-6 sdi command control register (sdiccon) register address r/w description reset value sdiccon 0x5a00000c r/w sdi command control register 0x0 sdiccon bit description initial value reserved [31:13] abort command (abortcmd) [12] determines whether command type is for abort(for sdio). 0 = normal command, 1 = abort command(cmd12, cmd52) 0 command with data (withdata) [11] determines whether command type is with data(for sdio). 0 = without data, 1 = with data 0 longrsp [10] determines whether host receives a 136-bit long response or not 0 = short response, 1 = long response 0 waitrsp [9] determines whether host waits for a response or not 0 = no response, 1 = wait response 0 command start(cmst) [8] determines whether command operation starts or not 0 = command ready, 1 = command start 0 cmdindex [7:0] command index with start 2bit(8bit) 0x00 sdi command status register (sdicsta) register address r/w description reset value sdicsta 0x5a000010 r/(c) sdi command status register 0x0 sdicsta bit description initial value reserved [31:13] response crc fail(rspcrc) [12] r/c crc check failed when command response received. this flag is cleared by setting to one this bit. 0 = not detect, 1 = crc fail 0 command sent (cmdsent) [11] r/c command sent(not concerned with response). this flag is cleared by setting to one this bit. 0 = not detect, 1 = command end 0 command time out (cmdtout) [10] r/c command response timeout(64clk). this flag is cleared by setting to one this bit. 0 = not detect, 1 = timeout 0 response receive end (rspfin) [9] r/c command response received. this flag is cleared by setting to one this bit. 0 = not detect, 1 = response end 0 cmd line progress on (cmdon) [8] command transfer in progress 0 = not detect, 1 = in progress 0 rspindex [7:0] response index 6bit with start 2bit(8bit) 0x00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X microprocessor sdi 19-7 sdi response register 0(sdirsp0) register address r/w description reset value sdirsp0 0x5a000014 r sdi response register 0 0x0 sdirsp0 bit description initial value response0 [31:0] card status[31:0](short), card status[127:96](long) 0x00000000 sdi response register 1(sdirsp1) register address r/w description reset value sdirsp1 0x5a000018 r sdi response register 1 0x0 sdirsp1 bit description initial value rcrc7 [31:24] crc7(with end bit, short), card status[95:88](long) 0x00 response1 [23:0] unused(short), card status[87:64](long) 0x000000 sdi response register 2(sdirsp2) register address r/w description reset value sdirsp2 0x5a00001c r sdi response register 2 0x0 sdirsp2 bit description initial value response2 [31:0] unused(short), card status[63:32](long) 0x00000000 sdi response register 3(sdirsp3) register address r/w description reset value sdirsp3 0x5a000020 r sdi response register 3 0x0 sdirsp3 bit description initial value response3 [31:0] unused(short), card status[31:0](long) 0x00000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. sdi S3C2440X risc microprocessor 19-8 sdi data / busy timer register(sdidtimer) register address r/w description reset value sdidtimer 0x5a000024 r/w sdi data / busy timer register 0x0 sdidtimer bit description initial value reserved [31:23] datatimer [22:0] data / busy timeout period 0x10000 sdi block size register(sdibsize) register address r/w description reset value sdibsize 0x5a000028 r/w sdi block size register 0x0 sdibsize bit description initial value reserved [31:12] blksize [11:0] block size value(0~4095 byte) , don?t care when stream mode 0x000 * in case of multi block, blksize must be aligned to word(4byte) size.(blksize[1:0] = 00)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X microprocessor sdi 19-9 sdi data control register(sdidcon) register address r/w description reset value sdidcon 0x5a00002c r/w sdi data control register 0x0 sdidcon bit description initial value reserved [31:22] sdio interrupt period type (prdtype) [21] determines whether sdio interrupt period is 2 cycle or extend more cycle when last data block is transferred(for sdio). 0 = exactly 2 cycle, 1 = more cycle(likely single block) 0 transmit after response (tarsp) [20] determines when data transmit start after response receive or not 0 = directly after datmode set, 1 = after response receive(assume datmode sets to 2?b11) 0 receive after command (racmd) [19] determines when data receive start after command sent or not 0 = directly after datmode set, 1 = after command sent (assume datmode sets to 2?b10) 0 busy after command (bacmd) [18] determines when busy receive start after command sent or not 0 = directly after datmode set, 1 = after command sent (assume datmode sets to 2?b01) 0 block mode (blkmode) [17] data transfer mode 0 = stream data transfer, 1 = block data transfer 0 wide bus enable (widebus) [16] determines enable wide bus mode 0 = standard bus mode(only sdidat[0] used), 1 = wide bus mode(sdidat[3:0] used) 0 dma enable (endma) [15] enable dma 0 = disable(polling), 1 = dma enable 0 stop by force (stop) [14] determines whether data transfer stop by force or not 0 = normal, 1 = stop by force 0 data transfer mode (datmode) [13:12] determines which direction of data transfer 00 = ready, 01 = only busy check start 10 = data receive start, 11 = data transmit start 00 blknum [11:0] block number(0~4095), don?t care when stream mode 0x000 notes : 1. if you want one of tarsp, racmd, bacmd bits(sdidcon[20:18]) to ?1?, you need to write on sdidcon register ahead of on sdiccon register.(always need for sdio) 2. when dma operation is completed, dma enable[15] bit of sdidcon register should be disabled.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. sdi S3C2440X risc microprocessor 19-10 sdi data remain counter register(sdidcnt) register address r/w description reset value sdidcnt 0x5a000030 r sdi data remain counter register 0x0 sdidcnt bit description initial value reserved [31:24] blknumcnt [23:12] remaining block number 0x000 blkcnt [11:0] remaining data byte of 1 block 0x000 sdi data status register(sdidsta) register address r/w description reset value sdidsta 0x5a000034 r/(c) sdi data status register 0x0 sdidsta bit description initial value reserved [31:11] read wait request occur (rwaitreq) [10] r/c read wait request signal transmits to sd card. the request signal is stopped and this flag is cleared by setting to one this bit. 0 = not occur, 1 = read wait request occur 0 sdio interrupt detect(iointdet) [9] r/c sdio interrupt detect. this flag is cleared by setting to one this bit. 0 = not detect, 1 = sdio interrupt detect 0 fifo fail error (fffail) [8] r/c fifo fail error when fifo occurs overrun / underrun / misaligned data saving. this flag is cleared by setting to one this bit. 0 = not detect, 1 = fifo fail 0 crc status fail(crcsta) [7] r/c crc status error when data block sent(crc check failed). this flag is cleared by setting to one this bit. 0 = not detect, 1 = crc status fail 0 data receive crc fail(datcrc) [6] r/c data block received error(crc check failed). this flag is cleared by setting to one this bit. 0 = not detect, 1 = receive crc fail 0 data time out(dattout) [5] r/c data / busy receive timeout. this flag is cleared by setting to one this bit. 0 = not detect, 1 = timeout 0 data transfer finish(datfin) [4] r/c data transfer completes(data counter is zero). this flag is cleared by setting to one this bit. 0 = not detect, 1 = data finish detect 0 busy finish (busyfin) [3] r/c only busy check finish. this flag is cleared by setting to one this bit 0 = not detect, 1 = busy finish detect 0 start bit error(sbiterr) [2] r/c start bit is not detected on all data signals in wide bus mode. this flag is cleared by setting to one this bit. 0 = not detect, 1 = command end 0 tx data progress on(txdaton) [1] data transmit in progress 0 = not active, 1 = data tx in progress 0 rx data progress on(rxdaton) [0] datareceiveinprogress 0 = not active, 1 = data rx in progress 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X microprocessor sdi 19-11 sdi fifo status register(sdifsta) register address r/w description reset value sdifsta 0x5a000038 r sdi fifo status register 0x0 sdifsta bit description initial state reserved [31:14] fifo available detect for tx (tfdet) [13] this bit indicates that fifo data is available for transmit when datmode is data transmit mode. if dma mode is enable, sd host requests dma operation. 0 = not detect(fifo full), 1 = detect(0 fifo 63) 0 fifo available detect for rx (rfdet) [12] this bit indicates that fifo data is available for receive when datmode is data receive mode. if dma mode is enable, sd host requests dma operation. 0 = not detect(fifo empty), 1 = detect(1 fifo 64) 0 tx fifo half full (tfhalf) [11] this bit sets to 1 whenever tx fifo is less than 33byte. 0=33 tx fifo 64, 1 = 0 tx fifo 32 0 tx fifo empty (tfempty) [10] this bit sets to 1 whenever tx fifo is empty. 0= 1 tx fifo 64, 1 = empty(0byte) 0 rx fifo last data ready (rflast) [9] this bit sets to 1 whenever rx fifo has last data of all block. 0 = not received yet, 1 = last data ready 0 rx fifo full (rffull) [8] this bit sets to 1 whenever rx fifo is full. 0= 0 rx fifo 63, 1 = full(64byte) 0 rx fifo half full (rfhalf) [7] this bit sets to 1 whenever rx fifo is more than 31byte. 0= 0 rx fifo 31, 1 = 32 rx fifo 64 0 fifo count (ffcnt) [6:0] number of data(byte) in fifo 0000000 sdi data register(sdidat) register address r/w description reset value sdidat 0x5a00003c(li/w, li/b, bi/w) 0x5a00003f(bi/b) r/w sdi data register 0x0 sdidat bit description initial state data register [31:0] this field contains the data to be transmitted or received over the sdi channel 0x00000000 * (li/w, li/b) : access by word/byte unit when endian mode is little * (bi/w) : access by word unit when endian mode is big * (bi/b) : access by byte unit when endian mode is big
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. sdi S3C2440X risc microprocessor 19-12 sdi interrupt mask register(sdiimsk) register address r/w description reset value sdiimsk 0x5a000040 r/w sdi interrupt mask register 0x0 sdicon bit description initial value reserved [31 : 18] rspcrc interrupt enable (rspcrcint) [17] determines sdi generate an interrupt if response crc check fails 0 = disable, 1 = interrupt enable 0 cmdsent interrupt enable (cmdsentint) [16] determines sdi generate an interrupt if command sent(no response required) 0 = disable, 1 = interrupt enable 0 cmdtout interrupt enable (cmdtoutint) [15] determines sdi generate an interrupt if command response timeout occurs 0 = disable, 1 = interrupt enable 0 rspend interrupt enable (rspendint) [14] determines sdi generate an interrupt if command response received 0 = disable, 1 = interrupt enable 0 rwaitreq interrupt enable (rwreqint) [13] determines sdi generate an interrupt if read wait request occur. 0 = disable, 1 = interrupt enable 0 iointdet interrupt enable (intdetint) [12] determines sdi generate an interrupt if sd host receives sdio interrupt from the card(for sdio). 0 = disable, 1 = interrupt enable 0 fffail interrupt enable (fffailint) [11] determines sdi generate an interrupt if fifo fail error occurs 0 = disable, 1 = interrupt enable 0 crcsta interrupt enable (crcstaint) [10] determines sdi generate an interrupt if crc status error o ccurs 0 = disable, 1 = interrupt enable 0 datcrc interrupt enable (datcrcint) [9] determines sdi generate an interrupt if data receive crc failed 0 = disable, 1 = interrupt enable 0 dattout interrupt enable (dattoutint) [8] determines sdi generate an interrupt if data receive timeout occurs 0 = disable, 1 = interrupt enable 0 datfin interrupt enable (datfinint) [7] determines sdi generate an interrupt if data counter is zero 0 = disable, 1 = interrupt enable 0 busyfin interrupt enable(busyfinint) [6] determines sdi generate an interrupt if only busy check completes 0 = disable, 1 = interrupt enable 0 sbiterr interrupt enable (sbiterrint) [5] determines sdi generate an interrupt if start bit error detect 0 = disable, 1 = interrupt enable 0 tfhalf interrupt enable (tfhalfint) [4] determines sdi generate an interrupt if tx fifo fills half 0 = disable, 1 = interrupt enable 0 tfempty interrupt enable(tfemptint) [3] determines sdi generate an interrupt if tx fifo is empty 0 = disable, 1 = interrupt enable 0 rflast interrupt enable (rflastint) [2] determines sdi generate an interrupt if rx fifo has last data 0 = disable, 1 = interrupt enable 0 rffull interrupt enable (rffullint) [1] determines sdi generate an interrupt if rx fifo fills full 0 = disable, 1 = interrupt enable 0 rfhalf interrupt enable (rfhalfint) [0] determines sdi generate an interrupt if rx fifo fills half 0 = disable, 1 = interrupt enable 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X microprocessor sdi 19-13 note
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor iic-bus interf a ce 20-1 iic-bus interface overview the S3C2440X risc microprocessor can support a multi-master iic-bus serial interface. a dedicated serial data line (sda) and a serial clock line (scl) carry information between bus masters and peripheral devices which are connected to the iic-bus. the sda and scl lines are bi-directional. in multi-master iic-bus mode, multiple S3C2440X risc microprocessors can receive or transmit serial data to or from slave devices. the master S3C2440X can initiate and terminate a data transfer over the iic-bus. the iic-bus in the S3C2440X uses standard bus arbitration procedure. to control multi-master iic-bus operations, values must be written to the following registers: ? multi-master iic-bus control register, iiccon ? multi-master iic-bus control/status register, iicstat ? multi-master iic-bus tx/rx data shift register, iicds ? multi-master iic-bus address register, iicadd when the iic-bus is free, the sda and scl lines should be both at high level. a high-to-low transition of sda can initiate a start condition. a low-to-high transition of sda can initiate a stop condition while scl remains steady at high level. the start and stop conditions can always be generated by the master devices. a 7-bit address value in the first data byte, which is put onto the bus after the start condition has been initiated, can determine the slave device which the bus master device has selected. the 8 th bit determines the direction of the transfer (read or write). every data byte put onto the sda line should be eight bits in total. the bytes can be unlimitedly sent or received during the bus transfer operation. data is always sent from most-significant bit (msb) first, and every byte should be immediately followed by acknowledge (ack) bit.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iic-bus interf a ce s3c2440 x risc microprocessor 20-2 pclk address register sda 4-bit prescaler iic-bus control logic iicstat iiccon comparator shift register shift register (iicds) data bus scl figure 20-1. iic-bus block diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor iic-bus interf a ce 20-3 iic-bus interface the S3C2440X iic-bus interface has four operation modes: ? master transmitter mode ? master receive mode ? slave transmitter mode ? slave receive mode functional relationships among these operating modes are described below. start and stop conditions when the iic-bus interface is inactive, it is usually in slave mode. in other words, the interface should be in slave mode before detecting a start condition on the sda line (a start condition can be initiated with a high-to-low transition of the sda line while the clock signal of scl is high). when the interface state is changed to master mode, a data transfer on the sda line can be initiated and scl signal generated. a start condition can transfer a one-byte serial data over the sda line, and a stop condition can terminate the data transfer. a stop condition is a low-to-high transition of the sda line while scl is high. start and stop conditions are always generated by the master. the iic-bus gets busy when a start condition is generated. a stop condition will make the iic-bus free. when a master initiates a start condition, it should send a slave address to notify the slave device. one byte of address field consists of a 7-bit address and a 1-bit transfer direction indicator (showing write or read). if bit 8 is 0, it indicates a write operation (transmit operation); if bit 8 is 1, it indicates a request for data read (receive operation). the master will finish the transfer operation by transmitting a stop condition. if the master wants to continue the data transmission to the bus, it should generate another start condition as well as a slave address. in this way, the read-write operation can be performed in various formats. scl sda sda scl start condition stop condition figure 20-2. start and stop condition
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iic-bus interf a ce s3c2440 x risc microprocessor 20-4 data transfer format every byte placed on the sda line should be eight bits in length. the bytes can be unlimitedly transmitted per transfer. the first byte following a start condition should have the address field. the address field can be transmitted by the master when the iic-bus is operating in master mode. each byte should be followed by an acknowledgement (ack) bit. the msb bit of the serial data and addresses are always sent first. notes: 1. s: start, rs: repeat start, p: stop, a: acknowledge 2. : from master to slave, : from slave to master writemodeformatwith7-bitaddresses "0" (write) data transferred (data + acknowledge) s slave address 7bits r/w a p data(1byte) a read mode format with 7-bit addresses "1" (read) data transferred (data + acknowledge) s slave address 7 bits r/w a p data a write mode format with 10-bit addresses "0" (write) data transferred (data + acknowledge) p data a s slave address 1st 7 bits r/w a slave address 2nd byte a 11110xx read mode format with 10-bit addresses "1" (read) s slave address 1st 7 bits 11110xx r/w a slave address 2nd byte a rs slave address 1st 7 bits a data transferred (data + acknowledge) p data a r/w "1" (read) figure 20-3. iic-bus interface data format
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor iic-bus interf a ce 20-5 sda acknowledgement signal from receiver scl s 1 2789 12 9 acknowledgement signal from receiver msb ack byte complete, interrupt within receiver clock line held low by receiver and/or transmitter figure 20-4. data transfer on the iic-bus ack signal transmission to complete a one-byte transfer operation, the receiver should send an ack bit to the transmitter. the ack pulse should occur at the ninth clock of the scl line. eight clocks are required for the one-byte data transfer. the master should generate the clock pulse required to transmit the ack bit. the transmitter should release the sda line by making the sda line high when the ack clock pulse is received. the receiver should also drive the sda line low during the ack clock pulse so that the sda keeps low during the high period of the ninth scl pulse. the ack bit transmit function can be enabled or disabled by software (iicstat). however, the ack pulse on the ninth clock of scl is required to complete the one-byte data transfer operation. data output by transmitter data output by receiver scl from master start condition clock pulse for acknowledgment clock to output 9 8 7 s 1 2 figure 20-5. acknowledge on the iic-bus
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iic-bus interf a ce s3c2440 x risc microprocessor 20-6 read-write operation in transmitter mode, when the data is transferred, the iic-bus interface will wait until iic-bus data shift (iicds) register receives a new data. before the new data is written into the register, the scl line will be held low, and then released after it is written. the S3C2440X should hold the interrupt to identify the completion of current data transfer. after the cpu receives the interrupt request, it should write a new data into the iicds register, again. in receive mode, when data is received, the iic-bus interface will wait until iicds register is read. before the new data is read out, the scl line will be held low and then released after it is read. the S3C2440X should hold the interrupt to identify the completion of the new data reception. after the cpu receives the interrupt request, it should read the data from the iicds register. bus arbitration procedures arbitration takes place on the sda line to prevent the contention on the bus between two masters. if a master with a sda high level detects the other master with a sda active low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. the arbitration procedure will be extended until the sda line turns high. however, when the masters simultaneously lower the sda line, each master should evaluate whether or not the mastership is allocated to itself. for the purpose of evaluation, each master should detect the address bits. while each master generates the slaver address, it should also detect the address bit on the sda line because the sda line is likely to get low rather than to keep high. assume that one master generates a low as first address bit, while the other master is maintaining high. in this case, both masters will detect low on the bus because the low status is superior to the high status in power. when this happens, low (as the first bit of address) generating master will get the mastership while high (as the first bit of address) generating master should withdraw the mastership. if both masters generate low as the first bit of address, there should be arbitration for the second address bit, again. this arbitration will continue to the end of last address bit. abort conditions if a slave receiver cannot acknowledge the confirmation of the slave address, it should hold the level of the sda line high. in this case, the master should generate a stop condition and to abort the transfer. if a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by canceling the generation of an ack after the last data byte received from the slave. the slave transmitter should then release the sda to allow a master to generate a stop condition. configuring iic-bus to control the frequency of the serial clock (scl), the 4-bit prescaler value can be programmed in the iiccon register. the iic-bus interface address is stored in the iic-bus address (iicadd) register. (by default, the iic-bus interface address has an unknown value.)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor iic-bus interf a ce 20-7 flowcharts of operations in each mode the following steps must be executed before any iic tx/rx operations. 1) write own slave address on iicadd register, if needed. 2) set iiccon register. a) enable interrupt b) define scl period 3) set iicstat to enable serial output write slave address to iicds. write 0xf0 (m/t start) to iicstat. thedataoftheiicdsis transmitted. ack period and then interrupt is pending. write 0xd0 (m/t stop) to iicstat. write new data transmitted to iicds. stop? clear pending bit to resume. thedataoftheiicdsis shiftedtosda. start master tx mode has been configured. clear pending bit . wait until the stop condition takes effect. end y n figure 20-6 operations for master/transmitter mode
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iic-bus interf a ce s3c2440 x risc microprocessor 20-8 write slave address to iicds. write0xb0(m/rstart) to iicstat. thedataoftheiicds(slave address) is transmitted. ack period and then interrupt is pending. write 0x90 (m/r stop) to iicstat. read a new data from iicds. stop? clear pending bit to resume. sda is shifted to iicds. start master rx mode has been configured. clear pending bit . wait until the stop condition takes effect. end y n figure 20-7 operations for master/receiver mode
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor iic-bus interf a ce 20-9 iic detects start signal. and, iicds receives data. iic compares iicadd and iicds (the received slave address). writedatatoiicds. the iic address match interrupt is generated. clear pending bit to resume. thedataoftheiicdsis shiftedtosda. start slave tx mode has been configured. end matched? n y stop? interrupt is pending. n y figure 20-8 operations for slave/transmitter mode
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iic-bus interf a ce s3c2440 x risc microprocessor 20-10 iic detects start signal. and, iicds receives data. iic compares iicadd and iicds (the received slave address). read data to iicds. the iic address match interrupt is generated. clear pending bit to resume. sda is shifted to iicds. start slave rx mode has been configured. end matched? n y stop? interrupt is pending. n y figure 20-9 operations for slave/receiver mode
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor iic-bus interf a ce 20-11 iic-bus interface special registers multi-master iic-bus control (iiccon) register register address r/w description reset value iiccon 0x54000000 r/w iic-bus control register 0x0x iiccon bit description initial state acknowledge generation (1) [7] iic-bus acknowledge enable bit. 0:disable 1:enable in tx mode, the iicsda is free in the ack time. in rx mode, the iicsda is l in the ack time. 0 tx clock source selection [6] source clock of iic-bus transmit clock prescaler selection bit. 0 : iicclk = f pclk /16 1 : iicclk = f pclk /512 0 tx/rx interrupt (5) [5] iic-bus tx/rx interrupt enable/disable bit. 0:disable, 1:enable 0 interrupt pending flag (2) (3) [4] iic-bus tx/rx interrupt pending flag. this bit cannot be written to 1. when this bit is read as 1, the iicscl is tied to l and the iic is stopped. to resume the operation, clear this bit as 0. 0 : 1) no interrupt pending (when read). 2) clear pending condition & resume the operation (when write). 1 : 1) interrupt is pending (when read) 2) n/a (when write) 0 transmit clock value (4) [3:0] iic-bus transmit clock prescaler. iic-bus transmit clock frequency is determined by this 4-bit prescaler value, according to the following formula: tx clock = iicclk/(iiccon[3:0]+1). undefined notes: 1. interfacing with eeprom, the ack generation may be disabled before reading the last data in order to generate the stop condition in rx mode. 2. an iic-bus interrupt occurs 1) when a 1-byte transmit or receive operation is completed, 2) when a general call or a slave address match occurs, or 3) if bus arbitration fails. 3. to adjust the setup time of iicsda before iisscl rising edge, iicds has to be written before clearing the iic interrupt pending bit. 4. iicclk is determined by iiccon[6]. tx clock can vary by scl transition time. when iiccon[6]=0, iiccon[3:0]=0x0 or 0x1 is not available. 5. if the iicon[5]=0, iicon[4] does not operate correctly. so, it is recommended that you should set iiccon[5]=1, although you does not use the iic interrupt.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iic-bus interf a ce s3c2440 x risc microprocessor 20-12 multi-master iic-bus control/status (iicstat) register register address r/w description reset value iicstat 0x54000004 r/w iic-bus control/status register 0x0 iicstat bit description initial state mode selection [7:6] iic-bus master/slave tx/rx mode select bits. 00 : slave receive mode 01 : slave transmit mode 10 : master receive mode 11 : master transmit mode 00 busy signal status / start stop condition [5] iic-bus busy signal status bit. 0 : read) not busy (when read) write) stop signal generation 1 : read) busy (when read) write) start signal generation. the data in iicds will be transferred automatically just after the start signal. 0 serial output [4] iic-bus data output enable/disable bit. 0 : disable rx/tx, 1 : enable rx/tx 0 arbitration status flag [3] iic-bus arbitration procedure status flag bit. 0 : bus arbitration successful 1 : bus arbitration failed during serial i/o 0 address-as-slave status flag [2] iic-bus address-as-slave status flag bit. 0 : cleared when start/stop condition was detected 1 : received slave address matches the address value in the iicadd 0 address zero status flag [1] iic-bus address zero status flag bit. 0 : cleared when start/stop condition was detected 1 : received slave address is 00000000b. 0 last-received bit status flag [0] iic-bus last-received bit status flag bit. 0 : last-received bit is 0 (ack was received). 1 : last-received bit is 1 (ack was not received). 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor iic-bus interf a ce 20-13 multi-master iic-bus address (iicadd) register register address r/w description reset value iicadd 0x54000008 r/w iic-bus address register 0xxx iicadd bit description initial state slave address [7:0] 7-bit slave address, latched from the iic-bus. when serial output enable = 0 in the iicstat, iicadd is write-enabled. the iicadd value can be read any time, regardless of the current serial output enable bit (iicstat) setting. slave address : [7:1] not mapped : [0] xxxxxxxx multi-master iic-bus transmit/receive data shift (iicds) register register address r/w description reset value iicds 0x5400000c r/w iic-bus transmit/receive data shift register 0xxx iicds bit description initial state data shift [7:0] 8-bit data shift register for iic-bus tx/rx operation. when serial output enable = 1 in the iicstat, iicds is write-enabled. the iicds value can be read any time, regardless of the current serial output enable bit (iicstat) setting. xxxxxxxx
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iic-bus interf a ce s3c2440 x risc microprocessor 20-14 multi-master iic-bus line control(iiclc) register register address r/w description reset value iiclc 0x54000010 r/w iic-bus multi-master line control register 0x00 iiclc bit description initial state filter enable [2] iic-bus filter enable bit. when sda port is operating as input, the filter enable bit should be high. this filter can prevent from occurred error by a glitch during double of pclk time. 0 : filter disable 1 : filter enable 0 sda output delay [1:0] iic-bus sda line delay length selection bits. it is delayed for following clock time(pclk) after high-to-low transition of scl line is occurred. then a high-to-low transition of the sda line will be occurred. 00 : 0 clocks 01 : 5 clocks 10:10clocks 11:15clocks 00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor iis-bus interface 21-1 21 iis-bus interface overview currently, many digital audio systems are attracting the consumers on the market, in the form of compact discs, digital audio tapes, digital sound processors, and digital tv sound. the S3C2440X inter-ic sound (iis) bus interface can be used to implement a codec interface to an external 8/16-bit stereo audio codec ic for mini- disc and portable applications. the iis bus interface supports both iis bus data format and msb-justified data format. the interface provides dma transfer mode for fifo access instead of an interrupt. it can transmit and receive data simultaneously as well as transmit or receive data alternatively at a time.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iis-bus interface S3C2440X risc microprocessor 21-2 block diagram addr data cntl pclk brfc ipsr_a ipsr_b txfifo rxfifo sclkg chnc sftr lrck sclk sd cdclk figure 21-1. iis-bus block diagram functional descriptions bus interface, register bank, and state machine (brfc): bus interface logic and fifo access are controlled by the state machine. 5-bit dual prescaler (ipsr): one prescaler is used as the master clock generator of the iis bus interface and the other is used as the external codec clock generator. 64-byte fifos (txfifo and rxfifo): in transmit data transfer, data are written to txfifo, and, in the receive data transfer, data are read from rxfifo. master iisclk generator (sclkg): in master mode, serial bit clock is generated from the master clock. channel generator and state machine (chnc): iisclk and iislrck are generated and controlled by the channel state machine. 16-bit shift register (sftr): parallel data is shifted to serial data output in the transmit mode, and serial data input is shifted to parallel data in the receive mode. transmit or receive only mode normal transfer iis control register has fifo ready flag bits for transmit and receive fifos. when fifo is ready to transmit data, the fifo ready flag is set to '1' if transmit fifo is not empty. if transmit fifo is empty, fifo ready flag is set to '0'. when receive fifo is not full, the fifo ready flag for receive fifo is set to '1' ; it indicates that fifo is ready to receive data. if receive fifo is full, fifo ready flag is set to '0'. these flags can determine the time that cpu is to write or read fifos. serial data can be transmitted or received while the cpu is accessing transmit and receive fifos in this way.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor iis-bus interface 21-3 dma transfer in this mode, transmit or receive fifo is accessible by the dma controller. dma service request in transmit or receive mode is made by the fifo ready flag automatically. transmit and receive mode in this mode, iis bus interface can transmit and receive data simultaneously. audio serial interface format iis-bus format the iis bus has four lines including serial data input (iisdi), serial data output (iisdo), left/right channel select (iislrck), and serial bit clock (iisclk); the device generating iislrck and iisclk is the master. serial data is transmitted in 2's complement with the msb first. the msb is transmitted first because the transmitter and receiver may have different word lengths. the transmitter does not have to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. when the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to '0') for data transmission. if the receiver gets more bits than its word length, the bits after the lsb are ignored. on the other hand, if the receiver gets fewer bits than its word length, the missing bits are set to zero internally. and therefore, the msb has a fixed position, whereas the position of the lsb depends on the word length. the transmitter sends the msb of the next word at one clock period whenever the iislrck is changed. serial data sent by the transmitter may be synchronized with either the trailing (high to low) or the leading (low to high) edge of the clock signal. however, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge. the lr channel select line indicates the channel being transmitted. iislrck may be changed either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. in the slave, this signal is latched on the leading edge of the clock signal. the iislrck line changes one clock period before the msb is transmitted. this allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. furthermore, it enables the receiver to store the previous word and clear the input for the next word. msb (left) justified msb / left justified bus format is the same as iis bus format architecturally. only, different from the iis bus format, the msb justified format realizes that the transmitter always sends the msb of the next word whenever the iislrck is changed.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iis-bus interface S3C2440X risc microprocessor 21-4 iis-bus format (n=8 or 16) msb (1st) 2nd bit n-1th bit lsb (last) msb (1st) 2nd bit n-1th bit lsb (last) msb (1st) lrck sclk sd left right left msb-justified format (n=8 or 16) 2nd bit n-1th bit lsb (last) msb (1st) 2nd bit n-1th bit lsb (last) lrck sclk sd left right msb (1st) figure 21-2. iis-bus and msb (left)-justified data interface formats sampling frequency and master clock master clock frequency (pclk) can be selected by sampling frequency as shown in table 21-1. because pclk is made by iis prescaler, the prescaler value and pclk type (256 or 384fs) should be determined properly. serial bit clock frequency type (16/32/48fs) can be selected by the serial bit per channel and pclk as shown in table 21-2. table 21-1 codec clock (codeclk = 256 or 384fs) iislrck (fs) 8.000 khz 11.025 khz 16.000 khz 22.050 khz 32.000 khz 44.100 khz 48.000 khz 64.000 khz 88.200 khz 96.000 khz 256fs codeclk 2.0480 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 (mhz) 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 table 21-2 usable serial bit clock frequency (iisclk = 16 or 32 or 48fs) serial bit per channel 8-bit 16-bit serial clock frequency (iisclk) @codeclk = 256fs 16fs, 32fs 32fs @codeclk = 384fs 16fs, 32fs, 48fs 32fs, 48fs
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor iis-bus interface 21-5 iis-bus interface special registers iis control (iiscon) register register address r/w description reset value iiscon 0x55000000 (li/hw, li/w, bi/w) 0x55000002 (bi/hw) r/w iis control register 0x100 iiscon bit description initial state left/right channel index (read only) [8] 0 = left 1 = right 1 transmit fifo ready flag (read only) [7] 0 = not ready (empty) 1 = ready (not empty) 0 receive fifo ready flag (read only) [6] 0 = not ready (full) 1 = ready (not full) 0 transmit dma service request [5] 0 = disable 1 = enable 0 receive dma service request [4] 0 = disable 1 = enable 0 transmit channel idle command [3] in idle state the iislrck is inactive (pause tx). 0=notidle 1=idle 0 receive channel idle command [2] in idle state the iislrck is inactive (pause rx). 0=notidle 1=idle 0 iis prescaler [1] 0 = disable 1 = enable 0 iis interface [0] 0 = disable (stop) 1 = enable (start) 0 notes: 1. the iiscon register is accessible for each byte, halfword and word unit using strb/strh/str and ldrb/ldrh/ldr instructions or char/short int/int type pointer in little/big endian mode. 2. (li/hw/w) : little/halfword/word (bi/hw/w) : big/halfword/word
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iis-bus interface S3C2440X risc microprocessor 21-6 iis mode register (iismod) register register address r/w description reset value iismod 0x55000004 (li/w, li/hw, bi/w) 0x55000006 (bi/hw) r/w iis mode register 0x0 iismod bit description initial state master/slave mode select [8] 0 = master mode (iislrck and iisclk are output mode). 1 = slave mode (iislrck and iisclk are input mode). 0 transmit/receive mode select [7:6] 00 = no transfer 01 = receive mode 10 = transmit mode 11 = transmit and receive mode 00 active level of left/right channel [5] 0 = low for left channel (high for right channel) 1 = high for left channel (low for right channel) 0 serial interface format [4] 0 = iis compatible format 1 = msb (left)-justified format 0 serial data bit per channel [3] 0 = 8-bit 1 = 16-bit 0 master clock frequency select [2] 0 = 256fs 1 = 384fs (fs : sampling frequency) 0 serial bit clock frequency select [1:0] 00 = 16fs 01 = 32fs 10 = 48fs 11 = n/a 00 notes: 1. the iismod register is accessible for each halfword and wordunit using strh/str and ldrh/ldr instructions or short int/int type pointer in little/big endian mode. 2. (li/hw/w) : little/halfword/word. (bi/hw/w) : big/halfword/word.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor iis-bus interface 21-7 iis prescaler (iispsr) register register address r/w description reset value iispsr 0x55000008 (li/hw, li/w, bi/w) 0x5500000a (bi/hw) r/w iis prescaler register 0x0 iispsr bit description initial state prescaler control a [9:5] data value: 0 ~ 31 note: prescaler a makes the master clock that is used the internal block and division factor is n+1. 00000 prescaler control b [4:0] data value: 0 ~ 31 note: prescaler b makes the master clock that is used the external block and division factor is n+1. 00000 notes: 1. the iispsr register is accessible for each byte, halfword and word unit using strb/strh/str and ldrb/ldrh/ldr instructions or char/short int/int type pointer in little/big endian mode. 2. (li/hw/w) : little/halfword/word. (bi/hw/w) : big/halfword/word.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. iis-bus interface S3C2440X risc microprocessor 21-8 iis fifo control (iisfcon) register register address r/w description reset value iisfcon 0x5500000c (li/hw, li/w, bi/w) 0x5500000e (bi/hw) r/w iis fifo interface register 0x0 iisfcon bit description initial state transmit fifo access mode select [15] 0 = normal 1=dma 0 receive fifo access mode select [14] 0 = normal 1=dma 0 transmit fifo [13] 0 = disable 1 = enable 0 receive fifo [12] 0 = disable 1 = enable 0 transmit fifo data count (read only) [11:6] data count value = 0 ~ 32 000000 receive fifo data count (read only) [5:0] data count value = 0 ~ 32 000000 notes: 1. the iisfcon register is accessible for each halfword and word unit using strh/str and ldrh/ldr instructions or short int/int type pointer in little/big endian mode. 2. (li/hw/w): little/halfword/word. (bi/hw/w): big/halfword/word. iis fifo (iisfifo) register iis bus interface contains two 16-byte fifo for the transmit and receive mode. each fifo has 16-width and 24- depth form, which allows the fifo to handles data for each halfword unit regardless of valid data size. transmit and receive fifo access is performed through fifo entry; the address of fentry is 0x55000010. register address r/w description reset value iisfifo 0x55000010(li/hw) 0x55000012(bi/hw) r/w iis fifo register 0x0 iisfif bit description initial state fentry [15:0] transmit/receive data for iis 0x0 notes: 1. the iisfifo register is accessible for each halfword and word unit using strh and ldrh instructions or short int type pointer in little/big endian mode. 2. (li/hw): little/halfword. (bi/hw): big/halfword.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor spi 22-1 22 spi overview the S3C2440X serial peripheral interface (spi) can interface the serial data transfer. the S3C2440X includes two spi, each of which has two 8-bit shift registers for transmission and receiving, respectively. during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). 8-bit serial data at a frequency is determined by its corresponding control register settings. if you only want to transmit, received data can be dummy. otherwise, if you only want to receive, you should transmit dummy '1' data. there are 4 i/o pin signals associated with spi transfers: the sck (spiclk0,1), the miso (spimiso0,1) data line, the mosi (spimosi0,1) data line, and the active low /ss (nss0,1) pin (input). features ? support 2-ch spi ? spi protocol (ver. 2.11) compatible ? 8-bit shift register for transmit ? 8-bit shift register for receive ? 8-bit prescaler logic ? polling, interrupt, and dma transfer mode ? 5v tolerant input (spi channel 1)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. spi S3C2440X risc microprocessor 22-2 block diagram 8bit prescaler 1 pclk status register 1 prescaler register 1 /ss nss 0 sck spiclk 0 mosi spimosi 0 miso spimiso 0 pin control logic 0 mstr tx 8bit shift reg 0 rx 8bit shift reg 0 lsb msb lsb msb 8 8 clock spi clock (master) cpol cpha clock logic 0 mulf dcol redy apb i/f 0 (int dma 0) master slave slave master slave slave master data bus int 0 / int 1 req0 / req1 ack0 / ack1 /ss nss 1 sck spiclk 1 mosi spimosi 1 miso spimiso 1 pin control logic 1 mstr tx 8bit shift reg 1 rx 8bit shift reg 1 lsb msb lsb msb 8 8 clock spi clock (master) cpol cpha clock logic 1 mulf dcol redy apb i/f 1 (int dma 1) master slave slave master slave slave master int 0 / int 1 req0 / req1 ack0 / ack1 8bit prescaler 0 pclk status register 0 prescaler register 0 figure 22-1. spi block diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor spi 22-3 spi operation using the spi interface, the S3C2440X can send/receive 8 ?bit data simultaneously with an external device. a serial clock line is synchronized with the two data lines for shifting and sampling of the information. when the spi is the master, transmission frequency can be controlled by setting the appropriate bit to sppren register. you can modify its frequency to adjust the baud rate data register value. when the spi is a slave, other master supplies the clock. when the programmer writes byte data to sptdatn register, spi transmit/receive operation will start simultaneously. in some cases, nss should be activated before writing byte data to sptdatn. programming procedure when a byte data is written into the sptdatn register, spi starts to transmit if ensck and mstr of spconn register are set. you can use a typical programming procedure to operate an spi card. to program the spi modules, follow these basic steps: 1. set baud rate prescaler register (sppren). 2. set spconn to configure properly the spi module. 3. write data 0xff to sptdatn 10 times in order to initialize mmc or sd card. 4. set a gpio pin, which acts as nss, to low to activate the mmc or sd card. 5. tx data check the status of transfer ready flag (redy=1), and then write data to sptdatn. 6. rx data(1): spconn's tagd bit disable = normal mode write 0xff to sptdatn, then confirm redy to set, and then read data from read buffer. 7. rx data(2): spconn's tagd bit enable = tx auto garbage data mode confirm redy to set, and then read data from read buffer(then automatically start to transfer). 8. set a gpio pin, which acts as nss, to high, to deactivate mmc or sd card.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. spi S3C2440X risc microprocessor 22-4 spi transfer format the S3C2440X supports 4 different format to transfer the data. figure 22-2 shows four waveforms for spiclk.. * lsb of previously transmitted character cycle mosi 1 2 3 4 5 6 7 8 msb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 lsb spiclk miso msb cpol = 1, cpha = 1 (format b) * msb of character just received cycle mosi 1 2 3 4 5 6 7 8 msb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 lsb msb * spiclk miso msb cpol = 1, cpha = 0 (format a) cycle mosi 1 2 3 4 5 6 7 8 6 5 4 3 2 1 lsb 6 5 4 3 2 1lsb * spiclk miso *lsb cpol = 0, cpha = 1 (format b) * msb of character just received cycle mosi 1 2 3 4 5 6 7 8 msb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 lsb msb * spiclk miso msb cpol = 0, cpha = 0 (format a) * lsb of previously transmitted character *lsb msb msb figure 22-2. spi transfer format
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor spi 22-5 transmitting procedure by dma 1. the spi is configured as dma mode. 2. dma is configured properly. 3. the spi requests dma service. 4. dma transmits 1byte data to the spi. 5. the spi transmits the data to card. 6. return to step 3 until dma count becomes 0. 7. the spi is configured as interrupt or polling mode with smod bits. receiving procedure by dma 1. the spi is configured as dma start with smod bits and setting tagd bit. 2. dma is configured properly. 3. the spi receives 1byte data from card. 4. the spi requests dma service. 5. dma receives the data from the spi. 6. write data 0xff automatically to sptdatn. 7. return to step 4 until dma count becomes 0. 8. the spi is configured as polling mode with smod bits and clearing tagd bit. 9. if spstan?s redy flag is set, then read the last byte data. note: total received data = dma tc values + the last data in polling mode (step 9). the first dma received data is dummy and so the user can neglect it.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. spi S3C2440X risc microprocessor 22-6 spi special registers spi control register register address r/w description reset value spcon0 0x59000000 r/w spi channel 0 control register 0x00 spcon1 0x59000020 r/w spi channel 1 control register 0x00 spconn bit description initial state spi mode select (smod) [6:5] determine how and by what sptdat is read/written. 00 = polling mode 01 = interrupt mode 10 = dma mode 11 = reserved 00 sck enable (ensck) [4] determine whether you want sck enable or not (for only master). 0 = disable 1 = enable 0 master/slave select (mstr) [3] determine the desired mode (master or slave). 0=slave 1=master note: in slave mode, there should be set up time for master to initiate tx/rx. 0 clock polarity select (cpol) [2] determine an active high or active low clock. 0 = active high 1 = active low 0 clock phase select (cpha) [1] select one of two fundamentally different transfer formats. 0 = format a 1 = format b 0 tx auto garbage data mode enable (tagd) [0] decide whether the receiving data only needs or not. 0 = normal mode 1 = tx auto garbage data mode note: in normal mode, if you only want to receive data, you should transmit dummy 0xff data. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor spi 22-7 spi status register register address r/w description reset value spsta0 0x59000004 r spi channel 0 status register 0x01 spsta1 0x59000024 r spi channel 1 status register 0x01 spstan bit description initial state reserved [7:3] data collision error flag (dcol) [2] this flag is set if the sptdatn is written or the sprdatn is read while a transfer is in progress and cleared by reading the spstan. 0 = not detect 1 = collision error detect 0 multi master error flag (mulf) [1] this flag is set if the nss signal goes to active low while the spi is configured as a master, and sppinn's enmul bit is multi master errors detect mode. mulf is cleared by reading spstan. 0 = not detect 1 = multi master error detect 0 transfer ready flag (redy) [0] this bit indicates that sptdatn or sprdatn is ready to transmit or receive. this flag is automatically cleared by writing data to sptdatn. 0 = not ready 1 = data tx/rx ready 1
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. spi S3C2440X risc microprocessor 22-8 spi pin control register when the spi system is enabled, the direction of pins, except nss pin, is controlled by mstr bit of spconn register. the direction of nss pin is always input. when the spi is a master, nss pin is used to check multi-master error, provided the sppin's enmul bit is active, and another gpio should be used to select a slave. if the spi is configured as a slave, the nss pin is used to select spi as a slave by one master. register address r/w description reset value sppin0 0x59000008 r/w spi channel 0 pin control register 0x02 sppin1 0x59000028 r/w spi channel 1 pin control register 0x02 sppinn bit description initial state reserved [7:3] multi master error detect enable (enmul) [2] the /ss pin is used as an input to detect multi master error when the spi system is a master. 0 = disable (general purpose) 1 = multi master error detect enable 0 reserved [1] this bit should be ?1?. 1 master out keep (keep) [0] determine mosi drive or release when 1byte transmit is completed (only master). 0 = release 1 = drive the previous level 0 the spimiso (miso) and spimosi (mosi) data pins are used for transmitting and receiving serial data. when the spi is configured as a master, spimiso (miso) is the master data input line, spimosi (mosi) is the master data output line, and spiclk (sck) is the clock output line. when the spi becomes a slave, these pins perform reversed roles. in a multiple-master system, spiclk (sck) pins, spimosi (mosi) pins, and spimiso (miso) pins are tied to configure a group respectively. a master spi can experience a multi master error, when other spi device working as a master selects the s3c2410 spi as a slave. when this error is detected, the following actions are taken immediately. but you must previously set sppinn?s enmul bit if you want to detect this error. 1. the spconn's mstr bit is forced to 0 to operate slave mode. 2. the spstan's mulf flag is set, and an spi interrupt is generated.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor spi 22-9 spi baud rate prescaler register register address r/w description reset value sppre0 0x5900000c r/w spi cannel 0 baud rate prescaler register 0x00 sppre1 0x5900002c r/w spi cannel 1 baud rate prescaler register 0x00 sppren bit description initial state prescaler value [7:0] determine spi clock rate as above equation. baud rate = pclk / 2 / (prescaler value + 1) 0x00 note : baud rate should be less than 25mhz. spi tx data register register address r/w description reset value sptdat0 0x59000010 r/w spi channel 0 tx data register 0x00 sptdat1 0x59000030 r/w spi channel 1 tx data register 0x00 sptdatn bit description initial state tx data register [7:0] this field contains the data to be transmitted over the spi channel. 0x00 spi rx data register register address r/w description reset value sprdat0 0x59000014 r spi channel 0 rx data register 0x00 sprdat1 0x59000034 r spi channel 1 rx data register 0x00 sprdatn bit description initial state rx data register [7:0] this field contains the data to be received over the spi channel. 0x00
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-1 camera interface overview this specification defines the interface of camera. the camera interface within S3C2440X consists of three parts. the one is the logic of catching camera input signals. the second one is the logic of format conversion and down scaling. and, the last one is the dedicated dma part. the camera interface supports itu bt.601/656 8-bit mode. the scaler of camera interface can scale down from below xga(up to horizontal 1016 pixels) input image into svga, vga, qvga, cif, qcif and any other smaller sizes. two master ports can be used variable applications like dsc, jpeg, mpeg self image and so on. camera interface can generate self test patterns as color bar, square box. it could be used in the calibration of image sync signals. also, video sync signals and pixel clock polarity can be inverted in camera interface by register setting.

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#$% figure 23-1. camera interface overview features ? supports itu-r bt.601/656 (4:2:2 ycbcr 8-bit mode). ? image down scaling capability for variable applications. ? two master port for dedicated dma operation. ? programmable the polarity of video sync signals. ? wide horizontal line buffer (maximum 1016 pixels). ? format conversion from ycbcr 4:2:2 to ycbcr 4:2:0 ? programmable burst length for dma operation.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-2 external interface camera interface in S3C2440X can support next itu video standard. ? itu bt.601 ycbcr 8-bit mode ? itu bt.656 ycbcr 8-bit mode signal description name i/o 1) active description pclk i - pixel clock, driven by the camera processor vsync i h vertical sync, driven by the camera processor href i h horizontal sync, driven by the camera processor data[7:0] i - pixel data for ycbcr, driven by the camera processor camclk o - master clock to the camera processor camrst o h software reset to the camera processor note 1) i/o direction is on the ap side. i : input, o : output, b : bi-direction table 23-1. camera interface signal description timing diagram vsync y cb y cr y cb y cb y cr href href (1h) pclk data[7:0] 1frame vertical lines horizontal width figure 23-2. itu-r bt.601 input timing diagram
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-3

figure 23-3. itu-r bt.656 input timing diagram there are two timing reference signals in itu-r bt.656 format, one at the beginning of each vedio data block (start of active video, sav) and one at the end of each video data block(end of active video, eav) as shown in figure 23-3 and table 23-2. data bit number first word (ff) second word (00) third word (00) forth word (xy) 9 (msb) 1 0 0 1 8 1 0 0 f 7 1 0 0 v 6 1 0 0 h 5 1 0 0 p3 4 1 0 0 p2 3 1 0 0 p1 2 1 0 0 p0 1(note1)1000 01000 note 1) for compatibility with existing 8-bit interfaces, the values of bits d1 and d0 are not defined. f = 0 (during field 1), 1 (during field 2) v = 0 (elsewhere), 1 (during field blanking) h = 0 (in sav : start of active video), 1 (in eav : end of active video) p0, p1, p2, p3 = protection bit table 23-2. video timing reference codes of itu-r bt.656 format camera interface logic can catch the video sync bits like h(sav,eav) and v(frame sync) after reserved data as ?ff-00-00?.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-4 camera interface operation two dma ports camif has two dma port. a-port and b-port are separated each other. at view of system bus, two ports are independent. the a-port stores the scale-downed and format-converted image to a-port ping-pong memories. the b-port stores the only format-converted image to b-port ping-pong memories. these two master ports enable variable application like dsc (digital steel camera), mpeg self image, etc. for example, a-port image can be used as preview image, and b-port image can be used as jpeg image in dsc application. also, a-port or b-port can be separately disabled.

figure 23-4. two dma ports
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-5 clock domain camif has three clock domains. the one is the system bus clock, which is hclk. another is the pixel clock, which is pclk. and, the other is the camera interface operation clock, which is op_clock. the system clock must be faster than any other clock. and, the pixel clock must be double speed compared to the operation clock of camera interface. as shown in figure 1-6, camclk must be divided from the fixed frequency like usb pll clock. op_clock has the half frequency of camclk.

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$%& ' $%(& figure 23-5. camif clock generation
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-6 frame memory hirerarchy frame memories consist of 4 ping-pong memories for each a- and b-ports. each ping-pong memory has three elements memory that is luminance, chrominance cb, and chrominance cr. after getting the input of itu format, camif transfers output data to ahb-bus for memory access. it is recommended that the arbitration priority of camif must be higher than other master except display controller. if ahb-bus is traffic enough that dma operation is not ending during one horizontal sync signal, it will enter into mal-function. so, the priority of camif must be separated to other round-robin priorities.

! ! ! ! " " " " # # # #$ $ $ $ % % % %# # # #& & & &# # # # ' ' ' ' ' ' ' ' ( ( ( ( ) ) ) ) * * * * + + + + , , , ,) ) ) )- - - - . .. .. .. . ' ' ' ' ' ' ' '$ $ $ $ ' ' ' ' ' ' ' '$ $ $ $ figure 23-6. ping-pong memory hierarchy
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-7 memory storing method the storing method to the frame memories is the little-endian method. the first entering pixels stored into lsb sides, and the last entering pixels stored into msb sides. the carried data by ahb bus is 32-bit word. so, camif make the each y-cb-cr words by little endian style. rightly, the carried data is the format-converted or scaled and format-converted data.

figure 23-7. memory storing style
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-8 timing diagram for register setting the first register setting for frame capture command can be occurred anytime in operation. for capturing fully occupied frame, the next frame must be captured. and, for another capture, you can program the second register setting in interrupt service routine. be sure that interrupt is flagged on the start of the captured frame period. one pulse interrupt signal can be programmed by irqfree of ctrl register as ?1?.

figure 23-8. timing diagram for register setting
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-9 software interface this camera interface provides a generic data-exchange method. but, you should keep in mind that write registers and read registers are separated. a-port sends scaled output to the ahb bus as in figure 23-1. b-port sends only format conversion or scaled output to the ahb bus. there is 4 ping-pong memories. consequently, 4 sets of y- cb-cr addresses exist. camera interface special registers 1. write register a image size register register address r/w description reset value asize 0x4f000000 w a-port image size 0xc8258 note) the base address is tbd asize bit description initial state ahsize [19:10] these bits indicate the horizontal pixel number of the target image for a-port. if target image size is qcif, these bits should be 10?d176, that is 10?hb0. 0x320 avsize [9:0] these bits indicate the vertical pixel number of the target image for a-port. if target image size is qcif, these bits should be 10?d144, that is 10?h90. 0x258 a y1 start address register register address r/w description reset value stay1 0x4f000004 r/w a-port image 1st ping-pong memory y start address 0xc073f000 stay1 bit description initial state stay1 [31:0] this register value will be the start address of luminance for 1 st ping-pong memory of a-port 0xc073f000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-10 a y2 start address register register address r/w description reset value stay2 0x4f000008 r/w a-port image 2nd ping-pong memory y start address 0xc07eec80 stay2 bit description initial state stay2 [31:0] this register value will be the start address of luminance for 2 nd ping-pong memory of a-port 0xc07eec80 a y3 start address register register address r/w description reset value stay3 0x4f00000c r/w a-port image 3rd ping-pong memory y start address 0xc089e900 stay3 bit description initial state stay3 [31:0] this register value will be the start address of luminance for 3 rd ping-pong memory of a-port 0xc089e900 a y4 start address register register address r/w description reset value stay4 0x4f000010 r/w a-port image 4th ping-pong memory y start address 0xc094e580 stay4 bit description initial state stay4 [31:0] this register value will be the start address of luminance for 4 th ping-pong memory of a-port 0xc094e580
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-11 a y burst register register address r/w description reset value ayburst 0x4f000014 w a-port image y data burst length 0x00000000 ayburst bit description initial state ayburst1 [31:16] these bits indicate main burst length of a-port during the memory read/write access for luminance data. 0x0000 ayburst2 [15:0] these bits indicate remained burst length of a-port during the memory read/write access for luminance data. 0x0000 * in cif case, ayburst1=8, ayburst2=8 are recommended. example 1. target image size : qcif (horizontal y width = 176 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 176 / 4 = 44 word. 44 % 8 = 4 main burst = 8, remained burst = 4 example 2. target image size : vga (horizontal y width = 640 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 640 / 4 = 160 word. 160 % 16 = 0 main burst = 16, remained burst = 16 a cb burst register register address r/w description reset value acbburst 0x4f000018 w a-port image cb data burst length 0x00000000 acbburst bit description initial state acbburst1 [31:16] these bits indicate main burst length of a-port during the memory read/write access for chrominance cb data. 0x0000 acbburst2 [15:0] these bits indicate remained burst length of a-port during the memory read/write access for chrominance cb data. 0x0000 * in cif case, acbburst1=4, acbburst2=4 are recommended. example 1. target image size : qcif (horizontal c width = 88 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 88 / 4 = 22 word. 22 % 4 = 2 main burst = 4, remained burst = 2 (internally two single operations) example 2. target image size : vga (horizontal c width = 320 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 320 / 4 = 80 word. 80 % 16 = 0 main burst = 16, remained burst = 16
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-12 a cr burst register register address r/w description reset value acrburst 0x4f00001c w a-port image cr data burst length 0x00000000 acrburst bit description initial state acrburst1 [31:16] these bits indicate main burst length of a-port during the memory read/write access for chrominance cr data. 0x0000 acrburst2 [15:0] these bits indicate remained burst length of a-port during the memory read/write access for chrominance cr data. 0x0000 * in cif case, acrburst1=4, acrburst2=4 are recommended. example 1. target image size : qcif (horizontal c width = 88 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 88 / 4 = 22 word. 22 % 4 = 2 main burst = 4, remained burst = 2 (internally two single operations) example 2. target image size : vga (horizontal c width = 320 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 320 / 4 = 80 word. 80 % 16 = 0 main burst = 16, remained burst = 16
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-13 b image size register register address r/w description reset value bsize 0x4f000020 w b-port image size 0xc8258 asize bit description initial state bhsize [19:10] these bits indicate the horizontal pixel number of the target image for b-port. if target image size is qcif, these bits should be 10?d176, that is 10?hb0. 0x320 bvsize [9:0] these bits indicate the vertical pixel number of the target image for b-port. if target image size is qcif, these bits should be 10?d144, that is 10?h90. 0x258 b y1 start address register register address r/w description reset value stby1 0x4f000024 w b-port image 1st ping-pong memory y start address 0xc073f000 stby1 bit description initial state stby1 [31:0] this register value will be the start address of luminance for 1 st ping-pong memory of b-port 0xc073f000 b y2 start address register register address r/w description reset value stby2 0x4f000028 w b-port image 2nd ping-pong memory y start address 0xc07eec80 stby2 bit description initial state stby2 [31:0] this register value will be the start address of luminance for 2 nd ping-pong memory of b-port 0xc07eec80
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-14 b y3 start address register register address r/w description reset value stby3 0x4f00002c w b-port image 3rd ping-pong memory y start address 0xc089e900 stby3 bit description initial state stby3 [31:0] this register value will be the start address of luminance for 3 rd ping-pong memory of b-port 0xc089e900 b y4 start address register register address r/w description reset value stby4 0x4f000030 w b-port image 4th ping-pong memory y start address 0xc094e580 stby4 bit description initial state stby4 [31:0] this register value will be the start address of luminance for 4 th ping-pong memory of b-port 0xc094e580 b y burst register register address r/w description reset value byburst 0x4f000034 w b-port image y data burst length 0x00000000 byburst bit description initial state byburst1 [31:16] these bits indicate main burst length of b-port during the memory read/write access for luminance data. 0x0000 byburst2 [15:0] these bits indicate remained burst length of b-port during the memory read/write access for luminance data. 0x0000 * in cif case, byburst1=8, byburst2=8 are recommended. example 1. target image size : qcif (horizontal y width = 176 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 176 / 4 = 44 word. 44 % 8 = 4 main burst = 8, remained burst = 4 example 2. target image size : vga (horizontal y width = 640 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 640 / 4 = 160 word. 160 % 16 = 0 main burst = 16, remained burst = 16
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-15 b cb burst register register address r/w description reset value bcbburst 0x4f000038 w b-port image cb data burst length 0x00000000 bcbburst bit description initial state bcbburst1 [31:16] these bits indicate main burst length of b-port during the memory read/write access for chrominance cb data. 0x0000 bcbburst2 [15:0] these bits indicate remained burst length of b-port during the memory read/write access for chrominance cb data. 0x0000 * in cif case, bcbburst1=4, bcbburst2=4 are recommended. example 1. target image size : qcif (horizontal c width = 88 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 88 / 4 = 22 word. 22 % 4 = 2 main burst = 4, remained burst = 2 (internally two single operations) example 2. target image size : vga (horizontal c width = 320 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 320 / 4 = 80 word. 80 % 16 = 0 main burst = 16, remained burst = 16 b cr burst register register address r/w description reset value bcrburst 0x4f00003c w b-port image cr data burst length 0x00000000 bcrburst bit description initial state bcrburst1 [31:16] these bits indicate main burst length of b-port during the memory read/write access for chrominance cr data. 0x0000 bcrburst2 [15:0] these bits indicate remained burst length of b-port during the memory read/write access for chrominance cr data. 0x0000 * in cif case, bcrburst1=4, bcrburst2=4 are recommended. example 1. target image size : qcif (horizontal c width = 88 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 88 / 4 = 22 word. 22 % 4 = 2 main burst = 4, remained burst = 2 (internally two single operations) example 2. target image size : vga (horizontal c width = 320 pixels. 1 pixel = 1 byte. 1 word = 4 pixel) 320 / 4 = 80 word. 80 % 16 = 0 main burst = 16, remained burst = 16
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-16 a last href distance width register register address r/w description reset value adistwidth 0x4f000040 w a-port distance and width for last hsync generation 0x1b581040 adistwidth bit description initial state adist [31:16] these bits indicate the distance from the start of external last href to the start of imitative href for last dma operation for a- port. adist = (tpclk/tsys) x 1.5 x h x 2 (tpclk : the period of incoming pixel clock, tsys : the period of system clock, h : the horizontal pixel number of source image) if you do not view the last horizontal line in your display, you should increase the number of adist by sufficient values. if it is not effective, contact the developer in samsung, please. 0x1b58 awidth [15:0] these bits indicate the width of imitative href for last dma operation for a-port. awidth = (tpclk/tsys) x 1.5 x h x 2 (tpclk : the period of incoming pixel clock, tsys : the period of system clock, h : the horizontal pixel number of source image) if you do not view the last horizontal line in your display, you should increase the number of adist by sufficient values. if it is not effective, contact the developer in samsung, please. 0x1040 example 1. source image size : vga (640 x 480), tpclk : 74ns (13.5mhz), tsys : 10ns (100mhz) adist = (74/10) x 1.5 x 640 x 2 = 14208 awidth = (74/10) x 1.5 x 640 x 2 = 14208
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-17 b last href distance width register register address r/w description reset value bdistwidth 0x4f000044 w b-port distance and width for last hsync generation 0x1b581040 adistwidth bit description initial state bdist [31:16] these bits indicate the distance from the start of external last href to the start of imitative href for last dma operation for b- port. bdist = (tpclk/tsys) x 1.5 x h x 2 (tpclk : the period of incoming pixel clock, tsys : the period of system clock, h : the horizontal pixel number of source image) if you do not view the last horizontal line in your display, you should increase the number of bdist by sufficient values. if it is not effective, contact the developer in samsung, please. 0x1b58 bwidth [15:0] these bits indicate the width of imitative href for last dma operation for b-port. bwidth = (tpclk/tsys) x 1.5 x h x 2 (tpclk : the period of incoming pixel clock, tsys : the period of system clock, h : the horizontal pixel number of source image) if you do not view the last horizontal line in your display, you should increase the number of bdist by sufficient values. if it is not effective, contact the developer in samsung, please. 0x1040 example 1. source image size : vga (640 x 480), tpclk : 74ns (13.5mhz), tsys : 10ns (100mhz) bdist = (74/10) x 1.5 x 640 x 2 = 14208 bwidth = (74/10) x 1.5 x 640 x 2 = 14208
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-18 y scale ratio register register address r/w description reset value yratio 0x4f00004c w a-port scaling ratio for luminace 0x14001400 yratio bit description initial state yhratio [31:16] (source y size / target y size) x 4096 0x1400 yvratio [15:0] (source y size / target y size) x 4096 0x1400 example 1. source image y size : vga (640 x 480), target image y size for a-port : qcif (176 x 144) yhratio = (640 / 176) x 4096 = 14894.545 ? 14894 (in round numbers) : 0x3a2e yvratio = (480 / 144) x 4096 = 13653.333 ? 13653 (in round numbers) : 0x3555 c scale ratio register register address r/w description reset value cratio 0x4f000050 w a-port scaling ratio for chrominace 0x14002800 cratio bit description initial state chratio [31:16] (source c size / target c size) x 4096 0x1400 cvratio [15:0] (source c size / target c size) x 4096 0x2800 example 1. source image c size : vga (320 x 480), target image c size for a-port : qcif (88 x 72) chratio = (320 / 88) x 4096 = 14894.545 ? 14894 (in round numbers) : 0x3a2e cvratio = (480 / 72) x 4096 = 27306.666 ? 27306 (in round numbers) : 0x6aaa
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-19 y original size register register address r/w description reset value yoriginal 0x4f000054 w yoriginalsize 0xc8258 yoriginal bit description initial state yoriginalx [25:16] these bits indicate the y horizontal size of source image. if input size is vga (640 x 480), yoriginalx should be 640. 0x320 yoriginaly [9:0] these bits indicate the y vertical size of source image. if input size is vga (640 x 480), yoriginaly should be 480. 0x258 c original size register register address r/w description reset value coriginal 0x4f00005c w c original size 0x64258 yoriginal bit description initial state coriginalx [25:16] these bits indicate the c horizontal size of source image. if input size is vga (640 x 480), coriginalx should be 320. 0x190 coriginaly [9:0] these bits indicate the c vertical size of source image. if input size is vga (640 x 480), coriginaly should be 480. 0x258 a cb1 start address register register address r/w description reset value stacb1 0x4f000074 w a-port image 1st ping-pong memory cb start address 0xc073f000 stacb1 bit description initial state stacb1 [31:0] this register value will be the start address of chrominace cb for 1 st ping-pong memory of a-port 0xc073f000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-20 a cb2 start address register register address r/w description reset value stacb2 0x4f000078 w a-port image 2nd ping-pong memory cb start address 0xc07eec80 stacb2 bit description initial state stacb2 [31:0] this register value will be the start address of chrominace cb for 2 nd ping-pong memory of a-port 0xc07eec80 a cb3 start address register register address r/w description reset value stacb3 0x4f00007c w a-port image 3rd ping-pong memory cb start address 0xc089e900 stacb3 bit description initial state stacb3 [31:0] this register value will be the start address of chrominace cb for 3 rd ping-pong memory of a-port 0xc089e900 a cb4 start address register register address r/w description reset value stacb4 0x4f000080 w a-port image 4th ping-pong memory cb start address 0xc094e580 stacb4 bit description initial state stacb4 [31:0] this register value will be the start address of chrominace cb for 4 th ping-pong memory of a-port 0xc094e580
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-21 a cr1 start address register register address r/w description reset value stacr1 0x4f000084 w a-port image 1st ping-pong memory cr start address 0xc073f000 stacr1 bit description initial state stacr1 [31:0] this register value will be the start address of chrominace cr for 1 st ping-pong memory of a-port 0xc073f000 a cr2 start address register register address r/w description reset value stacr2 0x4f000088 w a-port image 2nd ping-pong memory cr start address 0xc07eec80 stacr2 bit description initial state stacr2 [31:0] this register value will be the start address of chrominace cr for 2 nd ping-pong memory of a-port 0xc07eec80 a cr3 start address register register address r/w description reset value stacr3 0x4f00008c w a-port image 3rd ping-pong memory cr start address 0xc089e900 stacr3 bit description initial state stacr3 [31:0] this register value will be the start address of chrominace cr for 3 rd ping-pong memory of a-port 0xc089e900
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-22 a cr4 start address register register address r/w description reset value stacr4 0x4f000090 w a-port image 4th ping-pong memory cr start address 0xc094e580 stacr4 bit description initial state stacr4 [31:0] this register value will be the start address of chrominace cr for 4 th ping-pong memory of a-port 0xc094e580 b cb1 start address register register address r/w description reset value stbcb1 0x4f00009c w b-port image 1st ping-pong memory cb start address 0xc073f000 stbcb1 bit description initial state stbcb1 [31:0] this register value will be the start address of chrominace cb for 1 st ping-pong memory of b-port 0xc073f000 b cb2 start address register register address r/w description reset value stbcb2 0x4f0000a0 w b-port image 2nd ping-pong memory cb start address 0xc07eec80 stbcb2 bit description initial state stbcb2 [31:0] this register value will be the start address of chrominace cb for 2 nd ping-pong memory of b-port 0xc07eec80
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-23 b cb3 start address register register address r/w description reset value stbcb3 0x4f0000a4 w b-port image 3rd ping-pong memory cb start address 0xc089e900 stbcb3 bit description initial state stbcb3 [31:0] this register value will be the start address of chrominace cb for 3 rd ping-pong memory of b-port 0xc089e900 b cb4 start address register register address r/w description reset value stbcb4 0x4f0000a8 w b-port image 4th ping-pong memory cb start address 0xc094e580 stbcb4 bit description initial state stbcb4 [31:0] this register value will be the start address of chrominace cb for 4 th ping-pong memory of b-port 0xc094e580 b cr1 start address register register address r/w description reset value stbcr1 0x4f0000ac w b-port image 1st ping-pong memory cr start address 0xc073f000 stbcr1 bit description initial state stbcr1 [31:0] this register value will be the start address of chrominace cr for 1 st ping-pong memory of b-port 0xc073f000 b cr2 start address register register address r/w description reset value stbcr2 0x4f0000b0 w b-port image 2nd ping-pong memory cr start address 0xc07eec80 stbcr2 bit description initial state stbcr2 [31:0] this register value will be the start address of chrominace cr for 2 nd ping-pong memory of b-port 0xc07eec80
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-24 b cr3 start address register register address r/w description reset value stbcr3 0x4f0000b4 w b-port image 3rd ping-pong memory cr start address 0xc089e900 stbcr3 bit description initial state stbcr3 [31:0] this register value will be the start address of chrominace cr for 3 rd ping-pong memory of b-port 0xc089e900 b cr4 start address register register address r/w description reset value stbcr4 0x4f0000b8 w b-port image 4th ping-pong memory cr start address 0xc094e580 stbcr4 bit description initial state stbcr4 [31:0] this register value will be the start address of chrominace cr for 4 th ping-pong memory of b-port 0xc094e580
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-25 control register register address r/w description reset value ctrl 0x4f0000bc w camera interface control 0x00000000 ctrl bit description initial state softrst [30] this bit indicates software reset of camera interface. 1 = software reset 0 = normal 0 absame [29] this bit indicates which is same both a-port image and b-port image. if this bit is 1, a/b-port image will be the scaled images. 0 benas [20] this bit indicates the controllability of burst length for dma operations. 1 = software gives burst length 0 = self burst length generation 0 camrst [19] this bit indicates the software reset of external camera processor. 1 = software reset for camera processor 0 = normal 0 imgcapa [18] this bit indicates the image capture enable for a-port. if this bit set to 1, one clock pulse will be internally generated. 0 irqfree [17] this bit can clear the interrupt of camera interface. 1 = interrupt clear 0 = normal 0 testpt [16:14] these bits indicate the test pattern for verifying the incoming itu-r bt.601/656 sync signals and fundamental operations. 000 = bypass (external input) 001 = color-bar pattern 010 = square-box pattern 011 = solid-line pattern 100 = check pattern 101 = horizontal increasing pattern 110 = dc pattern 111 = reserved. 000 swapyuv [13] this bit controls the swap between y and uv sequence. 1=uyvy 0 = yuyv (recommended) 0 yuvord [12] this bit indicates y/uv order. it is recommended to fix 0. 0 uvoffset [11] this bit indicates the data offset of uv signals. 1 = offset binary 0 = normal (recommended) 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-26 hsyncpol [9] this bit indicates the polarity of incoming horizontal sync signal. 1 = inversion (low active) 0 = normal (high active) 0 vsyncpol [8] this bit indicates the polarity of incoming vertical sync signal. 1 = inversion (low active) 0 = normal (high active) 0 pclkpol [7] this bit indicates the polarity of incoming pixel clock signal. 1 = inversion (for not sufficient setup/hold timing) 0 = normal (recommended) 0 imgfmt [6] this bit indicates the format of input interface. 1 = itu-r bt.601 ycbcr 4:2:2 8-bit mode 0 = itu-r bt.656 ycbcr 4:2:2 8-bit mode 0 imgcapb [2] this bit indicates the image capture enable for b-port. if this bit set to 1, one clock pulse will be internally generated. 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-27 2. read register status read register register address r/w description reset value rdstat 0x4f000000 r camera interface status for cpu read 0x00000000 rdstat bit description initial state reserved [31:30] 00 rdfcnta [29:28] these bits indicate the count of 4 ping-pong frame memories for a-port. 00 = a-port 1 st frame 01 = a-port 2 nd frame 10 = a-port 3 rd frame 11 = a-port 4 th frame 00 rdfcntb [27:26] these bits indicate the count of 4 ping-pong frame memories for b-port. 00 = b-port 1 st frame 01 = b-port 2 nd frame 10 = b-port 3 rd frame 11 = b-port 4 th frame 00 rdcamrst [19] this bit indicates the software reset of external camera processor. 0 rdimgcapa [18] this bit indicates the enable state of a-port image capture sync to vsync signal. if capture is enabled, this bit will remain high to vync falling edge. 0 rdirqfree [17] this bit indicates the state of interrupt free. 1 = interrupt clear 0 = normal 0 rdtestpt [16:14] these bits indicate the test pattern for verifying the incoming itu-r bt.601/656 sync signals and fundamental operations. 000 = bypass (external input) 001 = color-bar pattern 010 = square-box pattern 011 = solid-line pattern 100 = check pattern 101 = horizontal increasing pattern 110 = dc pattern 111 = reserved. 000 rdswapyuv [13] this bit indicates the swap between y and uv sequence. 1=uyvy 0 = yuyv (recommended) 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-28 rdyuvord [12] this bit indicates y/uv order. it is recommended to fix 0. 0 rduvoffset [11] this bit indicates the data offset of uv signals. 1 = offset binary 0 = normal (recommended) 0 rdhsyncpol [9] this bit indicates the polarity of incoming horizontal sync signal. 1 = inversion (low active) 0 = normal (high active) 0 rdvsyncpol [8] this bit indicates the polarity of incoming vertical sync signal. 1 = inversion (low active) 0 = normal (high active) 0 rdpclkpol [7] this bit indicates the polarity of incoming pixel clock signal. 1 = inversion (for not sufficient setup/hold timing) 0 = normal (recommended) 0 rdimgfmt [6] this bit indicates the format of input interface. 1 = itu-r bt.601 ycbcr 4:2:2 8-bit mode 0 = itu-r bt.656 ycbcr 4:2:2 8-bit mode 0
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-29 a y start address read register register address r/w description reset value rdstay 0x4f000014 r a-port image current y start address 0x00000000 rdstay bit description initial state rdstay [31:0] this register value indicates the current start address of luminance for a-port 0x00000000 a cb start address read register register address r/w description reset value rdstacb 0x4f000018 r a-port image current cb start address 0x00000000 rdstacb bit description initial state rdstacb [31:0] this register value indicates the current start address of chrominance cb for a-port 0x00000000 a cr start address read register register address r/w description reset value rdstacr 0x4f00001c r a-port image current cr start address 0x00000000 rdstacr bit description initial state rdstacr [31:0] this register value indicates the current start address of chrominance cr for a-port 0x00000000 a cb1 start address read register register address r/w description reset value rdstacb1 0x4f000020 r a-port image 1st ping-pong memory cb start address 0xc073f000 rdstacb1 bit description initial state rdstacb1 [31:0] this register value indicates the start address of chrominance cb for 1 st ping-pong memory of a-port 0xc073f000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-30 a cr1 start address read register register address r/w description reset value rdstacr1 0x4f000024 r a-port image 1st ping-pong memory cr start address 0xc073f000 rdstacr1 bit description initial state rdstacr1 [31:0] this register value indicates the start address of chrominance cr for 1 st ping-pong memory of a-port 0xc073f000 b y1 start address read register register address r/w description reset value rdstby1 0x4f000028 r b-port image 1st ping-pong memory y start address 0xc073f000 rdstby1 bit description initial state rdstby1 [31:0] this register value indicates the start address of luminance for 1 st ping-pong memory of b-port 0xc073f000 b y2 start address read register register address r/w description reset value rdstby2 0x4f00002c r b-port image 2nd ping-pong memory y start address 0xc07eec80 rdstby2 bit description initial state rdstby2 [31:0] his register value indicates the start address of luminance for 2 nd ping-pong memory of b-port 0xc07eec80 b y3 start address read register register address r/w description reset value rdstby3 0x4f000030 r b-port image 3rd ping-pong memory y start address 0xc089e900 rdstby3 bit description initial state rdstby3 [31:0] his register value indicates the start address of luminance for 3 rd ping-pong memory of b-port 0xc089e900
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-31 b y4 start address read register register address r/w description reset value rdstby4 0x4f000034 r b-port image 4th ping-pong memory y start address 0xc094e580 rdstby4 bit description initial state rdstby4 [31:0] his register value indicates the start address of luminance for 4 th ping-pong memory of b-port 0xc094e580 b y start address read register register address r/w description reset value rdstby 0x4f000038 r b-port image current y start address 0x00000000 rdstby bit description initial state rdstby [31:0] this register value indicates the current start address of luminance for b-port 0x00000000 b cb start address read register register address r/w description reset value rdstbcb 0x4f00003c r b-port image current cb start address 0x00000000 rdstbcb bit description initial state rdstbcb [31:0] this register value indicates the current start address of chrominance cb for b-port 0x00000000 b cr start address read register register address r/w description reset value rdstbcr 0x4f000040 r b-port image current cr start address 0x00000000 rdstbcr bit description initial state rdstbcr [31:0] this register value indicates the current start address of chrominance cr for b-port 0x00000000
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. camera interface S3C2440X risc microprocessor 23-32 b cb1 start address read register register address r/w description reset value rdstbcb1 0x4f000044 r b-port image 1st ping-pong memory cb start address 0xc073f000 rdstbcb1 bit description initial state rdstbcb1 [31:0] this register value indicates the start address of chrominance cb for 1 st ping-pong memory of b-port 0xc073f000 b cr1 start address read register register address r/w description reset value rdstbcr1 0x4f000048 r b-port image 1st ping-pong memory cr start address 0xc073f000 rdstbcr1 bit description initial state rdstbcr1 [31:0] this register value indicates the start address of chrominance cr for 1 st ping-pong memory of b-port 0xc073f000 a last href distance width read register register address r/w description reset value rdadistwidth 0x4f00004c r a-port distance and width for last hsync generation 0x1b581040 rdadistwidth bit description initial state rdadist [31:16] these bits indicate the distance from the start of external last href to the start of imitative href for last dma operation for a- port. 0x1b58 rdawidth [15:0] these bits indicate the width of imitative href for last dma operation for a-port. 0x1040
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor camera interface 23-33 b last href distance width read register register address r/w description reset value rdbdistwidth 0x4f000050 r b-port distance and width for last hsync generation 0x1b581040 rdbdistwidth bit description initial state rdbdist [31:16] these bits indicate the distance from the start of external last href to the start of imitative href for last dma operation for b- port. 0x1b58 rdbwidth [15:0] these bits indicate the width of imitative href for last dma operation for b-port. 0x1040
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor bus priorities 24-1 bus priorities overview the bus arbitration logic determines the priorities of bus masters. it supports a combination of rotation priority mode and fixed priority mode. bus priority map the S3C2440X01 holds eleven bus masters including dram refresh controller, lcd_dma, dma0, dma1, dma2, dma3, usb_host_dma, ext_bus_master, test interface controller (tic), and arm920t. the following list shows the priorities among these bus masters after a reset: 1. dram refresh controller 2. lcd_dma 3. dma0 4. dma1 5. dma2 6. dma3 7. usb host dma 8. external bus master 9. tic 10. arm920t 11. reserved among those bus masters, four dmas operate under the rotation priority, while others run under the fixed priority.
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. bus priorities s3c2440 x risc microprocessor 24-2 notes
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-1 25 electrical data absolute maximum ratings table 25-1. absolute maximum rating parameter symbol rating unit dc supply voltage v ddi 1.2v v dd 1.8 v ddio 3.3v v dd 4.8 v ddrtc 3.0v v dd 4.5 dc input voltage v in 3.3v input buffer 4.8 v 3.3v interface / 5v tolerant input buffer 6.5 dc output voltage v out 3.3v output buffer 4.8 dc input (latch-up) current i in 200 ma storage temperature t stg ? 65 to 150 o c recommended operating conditions table 25-2. recommended operating conditions rating parameter symbol min max unit dc supply voltage for internal v ddi 1.2v v dd 1.1 1.3 dc supply voltage for i/o block v ddio 3.3v v dd 3.0 3.6 dc supply voltage for analog core v dd 3.3v v dd 3.0 3.6 dc supply voltage for rtc v ddrtc 3.0v v dd 2.7 3.6 dc input voltage v in 3.3v input buffer ? 0.3 vddio+0.3 v 3.3v interface / 5v tolerant input buffer ? 0.3 5.25 dc output voltage v out 3.3v output buffer ? 0.3 vddio+0.3 operating temperature t opr commercial 0 to 70 o c
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-2 d.c. electrical characteristics table 25-3 and 25-4 define the dc electrical characteristics for the standard lvcmos i/o buffers. table 25-3. normal i/o pad dc electrical characteristics (v dd =3.3v 0.3v, t a =0to70 c) symbol parameters condition min type max unit v ih high level input voltage lvcmos interface 2.0 v v il low level input voltage lvcmos interface 0.8 v vt switching threshold 0.5v dd v vt+ schmitt trigger, positive-going threshold cmos 2.0 v vt- schmitt trigger, negative-going threshold cmos 0.8 v i ih high level input current input buffer v in =v dd -10 10 a i il low level input current input buffer v in =v ss -10 10 a input buffer with pull-up -60 -33 -10 v oh high level output voltage type b4 i oh =-4ma type b6 i oh =-6ma type b8 i oh =-8ma 2.4 v type b10 i oh =-10ma type b12 i oh =-12ma v ol low level output voltage type b4 i ol =4ma type b6 i ol =6ma type b8 i ol =8ma 0.4 v type b10 i ol =10ma type b12 i ol =12ma notes: 1. type b6 means 6ma output driver cell. 2. type b8 means 8ma output driver cell. 3. type b12 means 12ma output driver cells.
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-3 table 25-4. usb dc electrical characteristics symbol parameter condition min max unit v ih high level input voltage 2.5 v v il low level input voltage 0.8 v i ih high level input current vin = 3.3v -10 10 a i il low level input current vin = 0.0v -10 10 a v oh static output high 15k to gnd 2.8 3.6 v v ol static output low 1.5k to 3.6v 0.3 v table 25-5. S3C2440X power supply voltage and current parameter value unit condition typical v ddi /v ddio 1.2 / 3.3 v max. operating frequency (fclk) 400 mhz max. operating frequency (hclk) 133 mhz max. operating frequency (pclk) 67 mhz typical normal mode power note(3) (total v ddi +v ddio ) 369 mw note(1) typical normal mode power note(3) (total v ddi +v ddio ) 266 mw note(2) typical idle mode power note(3) (total v ddi +v ddio ) 172 mw fclk = 400mhz (f:h:p = 1:3:6) typical slow mode power note(3) (total v ddi +v ddio ) 97 mw fclk = 12mhz (f:h:p = 1:1:1) maximum sleep mode power typical sleep mode power note(3) 100 10 ua ua @1.2/3.3v, room temperature all other i/o static. maximum rtc power typical rtc power note(3) 63 4 ua ua @3.0v, room temperature x-tal = 32.768khz for rtc notes: 1. i/d cache: on, mmu: on, code on sram, fclk:hclk:pclk = 400mhz:133mhz:66.7mhz :lcd on (320x240x16bppx60hz, color tft):13khz timer internal mode(5 channel run) :audio(iis&dma,cdclk=16.9mhz,lrck=44.1khz):integer data quick sort(65536 ea) 2. pocket pc 2003 mpeg play. 3. room temperature specification.
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-4 table 25-6. typical current decrease by clkcon register (fclk@400mhz) (unit: ma) peripherals nfc lcd usbh usbd timer sdi uart rtc adc iic iis spi total current note: this table includes each power consumption of each peripherals. for example, if you do not use iis and you turned off iis block by clkcon register, you can save the 0.5ma . figure 25-1. typical operating voltage/frequency range (vddio=3.3v, @room temperature & smdk2440 board)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-5 a.c. electrical characteristics 1/2 v dd 1/2 v dd t xtalcyc note: the clock input from the x tipll pin. figure 25-2. xtipll clock timing t exthigh v ih 1/2 v dd v il v il v ih v ih 1/2 v dd t extlow t extcyc note: the clock input from the extclk pin. figure 25-3. extclk clock input timing hclk (internal) extclk t ex2hc figure 25-4. extclk/hclk in case that extclk is used without the pll
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-6 hclk (internal) sclk clkout (hclk) t hc2ck t hc2sclk figure 25-5. hclk/clkout/sclk in case that extclk is used extclk t resw nreset figure 25-6. manual reset input timing
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-7 nreset xtipll or extclk vco output mcu operates by xtipll or extclk clcok. clock disable tpll fclk is new frequency. power pll can operate after om[3:2] is latched. pll is configured by s/w first time. vco is adapted to new clock frequency. fclk ... ... ... trst2run figure 25-7. power-on oscillation setting timing
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-8 xtipll vco output clock disable fclk several slow clocks (xtipll or extclk) power_off mode is initiated. t osc2 extclk figure 25-8. sleep mode return oscillation setting timing
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-9 hclk ngcsx trad noe data addr nbex trcd trod trod trcd tacc trad trad trad trad trad trad trad trad trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh '1' figure 25-9. rom/sram burst read timing(i) (tacs=0, tcos=0, tacc=2, toch=0, tcah=0, pmc=0, st=0, dw=16bit)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-10 hclk ngcsx trad noe data addr nbex trcd trod trod trcd trbed trbed tacc trad trad trad trad trad trad trad trad trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh figure 25-10. rom/sram burst read timing(ii) (tacs=0, tcos=0, tacc=2, toch=0, tcah=0, pmc=0, st=1, dw=16bit)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-11 hclk ngs noe addr txnbrqs xnbreq txnbrqh xnback 'hz' 'hz' 'hz' txnbackd txnbackd thzd thzd thzd figure 25-11. external bus request in rom/sram cycle (tacs=0, tcos=0, tacc=8, toch=0, tcah=0, pmc=0, st=0)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-12 hclk ngcsx trad tacs noe tcos data addr nwbex '1' toch tcah trcd trod trds trdh trod trcd trad tacc figure 25-12. rom/sram read timing (i) (tacs=2,tcos=2, tacc=4, toch=2, tcah=2, pmc=0, st=0)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-13 hclk ngcsx trad tacs noe tcos data addr nbex toch tcah trcd trod trds trdh trod trcd trad trbed trbed tacc figure 25-13. rom/sram read timing (ii) (tacs=2, tcos=2, tacc=4, toch=2, tcah=2cycle, pmc=0, st=1)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-14 hclk ngcsx trad tacs nwe tcos data addr nwbex toch tcah trcd trwd trdd trwd trcd trad tcos toch trwbed trwbed tacc trdd figure 25-14. rom/sram write timing (i) (tacs=2,tcos=2,tacc=4,toch=2, tcah=2, pmc=0, st=0
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-15 hclk ngcsx trad tacs nwe tcos data addr nbex toch tcah trcd trwd trdd trwd trcd trad trbed trbed tacc trdd figure 25-15. rom/sram write timing (ii) (tacs=2, tcos=2, tacc=4, toch=2, tcah=2, pmc=0, st=1)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-16 hclk ngcsx noe tacc = 6cycle nwait data addr tacs tacs delayed trc note: the status of nwait is checked at (tacc-1) cycle. sampling nwait figure 25-16. external nwait read timing (tacs=0, tcos=0, tacc=6, toch=0, tcah=0, pmc=0, st=0) hclk ngcsx nwe data addr trdd trdd tacc >= 2cycle nwait tws twh figure 25-17. external nwait write timing (tacs=0, tcos=0, tacc=4, toch=0, tcah=0, pmc=0, st=0)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-17 hclk ngcsx trad tacs noe tcos data addr trcd trod trds trdh trad tacc figure 25-18. masked-rom single read timing (tacs=2, tcos=2, tacc=8, pmc=01/10/11) hclk ngcsx trad noe data addr trcd trod trds trdh trad tacc tpac tpac tpac tpac trad trad trad trad trds trdh trds trdh trds trdh trds trdh figure 25-19. masked-rom consecutive read timing (tacs=0, tcos=0, tacc=3, tpac=2, pmc=01/10/11)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-18 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsds tsdh scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' trcd tsbed tcl figure 25-20. sdram single burst read timing (trp=2, trcd=2, tcl=2, dw=16bit)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-19 sclk nsras nscas addr/ba nbex txnbrqh txnbrqs scke a10/ap ngcsx nwe '1' xnbreq xnback extclk txnbackd txnbackd 'hz' 'hz' 'hz' 'hz' 'hz' 'hz' 'hz' 'hz' 'hz' thzd thzd thzd thzd thzd thzd thzd thzd thzd txnbrql figure 25-21. external bus request in sdram timing (trp=2, trcd=2, tcl=2)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-20 sclk nsras tsad nscas data addr/ba nbex tsrd scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' tsad tscsd tsrd 'hz' '1' tswd figure 25-22. sdram mrs timing
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-21 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsds tsdh scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' tsad tsad trcd tscsd tsrd tscsd tsad tsad tsbed tcl figure 25-23. sdram single read timing(i) (trp=2, trcd=2, tcl=2)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-22 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsds tsdh scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' tsad tsad trcd tscsd tsrd tscsd tsad tsad tsbed tcl figure 25-24. sdram single read timing(ii) (trp=2, trcd=2, tcl=3)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-23 sclk nsras tsad trp nscas data addr/ba nbex tsrd scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' tsad tscsd tsrd '1' '1' 'hz' trc note: before executing auto/self refresh command, all banks must be in idle state. figure 25-25. sdram auto refresh timing (trp=2, trc=4)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-24 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsds tsdh scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' trcd tsbed tcl tcl tcl figure 25-26. sdram page hit-miss read timing (trp=2, trcd=2, tcl=2)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-25 sclk nsras tsad trp nscas data addr/ba nbex tsrd scke a10/ap ngcsx tscsd nwe tsad tscd tswd tsad tscsd tsrd '1' '1' 'hz' trc tcked 'hz' '1' '1' '1' '1' '1' tcked note: before executing auto/self refresh command, all banks must be in idle state. figure 25-27. sdram self refresh timing (trp=2, trc=4)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-26 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsdd tsdd scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' tsad tsad trcd tscsd tsrd tscsd tsad tsad tsbed figure 25-28. sdram single write timing (trp=2, trcd=2)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-27 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsdd tsdd scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' trcd tsbed figure 25-29. sdram page hit-miss write timing (trp=2, trcd=2, tcl=2)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-28 xsclk txrs txrs tcadl tcadh txad xnxdreq xnxdack read write min. 3sclk figure 25-30. external dma timing (handshake, single transfer) vsync hsync vden tf2hsetup tf2hhold tvspw tvbpd tvfpd hsync vclk vd vden lend tl2csetup tvclkh tvclk tvclkl tvdhold tvdsetup tve2hold tle2chold tlewidth figure 25-31. tft lcd controller timing
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-29 iissclk tlrck iislrck (out) tsdo iislrck (out) tsdih tsdis iissdi (in) figure 25-32. iis interface timing tstoph tstarts tsdas tsdah tbuf tsclhigh tscllow fscl iicscl iicsda figure 25-33. iic interface timing
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-30 sdclk tsdcd sdcmd (out) tsdch tsdcs tsddd sdcmd (in) tsddh tsdds sddata[3:0] (in) sddata[3:0] (out) figure 25-34. sd/mmc interface timing spiclk tspimod tspisih tspisis tspisod tspimih tspimis spimosi (mo) spimosi (si) spimiso (so) spimiso (mi) figure 25-35. spi interface timing (cpha=1, cpol=1)
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-31 tacls twrph0 twrph1 command twrph0 twrph1 address hclk ale nfwe data[7:0] data[7:0] hclk cle nfwe tcled tcled twed twed twds twdh taled twed twds taled twed twdh tacls figure 25-36. nand flash address/command timing hclk nfwe twrph0 twrph1 data[7:0] hclk nfre twrph0 twrph1 data[7:0] twed twed twdh twed twed trds trdh twds wdata rdata figure 25-37. nand flash timing
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-32 table 25-7. clock timing constants (v ddi, v ddalive, v ddiarm =1.2v 0.1 v ,t a =0to70 c, v ddmop =3.3v 0.3v) parameter symbol min typ max unit crystal clock input frequency f xtal 10?20 mhz crystal clock input cycle time t xtalcyc 50 ? 100 ns external clock input frequency f ext ??66 mhz external clock input cycle time t extcyc 15.0 ? ? ns external clock input low level pulse width t extlow 7?? ns external clock to hclk (without pll) t ex2hc 3?7 ns hclk (internal) to clkout t hc2ck 3?8 ns hclk (internal) to sclk t hc2sclk 0?1 ns external clock input high level pulse width t exthigh 4?? ns reset assert time after clock stabilization t resw 4?? xtipll or extclk pll lock time t pll 300 ? us sleep mode return oscillation setting time t osc2 ? ? 65536 xtipll or extclk the interval before cpu runs after nreset is released. t rst2run ?7? xtipll or extclk
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-33 table 25-8. rom/sram bus timing constants (v ddi, v ddalive, v ddiarm = 1.2 v 0.1 v ,t a =0to70 c, v ddmop =3.3v 0.3v) parameter symbol min typ max unit rom/sram address delay t rad 3?7 ns rom/sram chip select delay t rcd 2?7 ns rom/sram output enable delay t rod 2?5 ns rom/sram read data setup time. t rds 1?3 ns rom/sram read data hold time. t rdh 0?1 ns rom/sram byte enable delay t rbed 2?6 ns rom/sram write byte enable delay t rwbed 2?6 ns rom/sram output data delay t rdd 2?7 ns rom/sram external wait setup time t ws 1?3 ns rom/sram external wait hold time t wh 0?1 ns rom/sram write enable delay t rwd 3?6 ns table 25-9. memory interface timing constants (3.3v) (v ddi, v ddalive, v ddiarm = 1.2 v 0.1 v ,t a =0to70 c, v ddmop =3.3v 0.3v) parameter symbol min typ max unit sdram address delay t sad 2?7 ns sdram chip select delay t scsd 2?5 ns sdram row active delay t srd 2?5 ns sdram column active delay t scd 2?5 ns sdram byte enable delay t sbed 2?6 ns sdram write enable delay t swd 2?6 ns sdram read data setup time t sds 1?3 ns sdram read data hold time t sdh 0?1 ns sdram output data delay t sdd 2?8 ns sdram clock enable delay t cked 2?5 ns
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-34 table 25-10. external bus request timing constants (v dd = 1.2 v 0.1 v ,t a =0to70 c, v ext =3.3v 0.3v) parameter symbol min typ. max unit external bus request setup time t xnbrqs 2?4 ns external bus request hold time t xnbrqh 0?1 ns external bus ack delay t xnbackd 4?10 ns hz delay t hzd 3?8 ns table 25-11. dma controller module signal timing constants (v dd = 1.2 v 0.1 v ,t a =0 to 70 c, v ext =3.3v 0.3v) parameter symbol min typ. max unit external request setup t xrs 2?4 ns access to ack delay when low transition t cadl 4?9 ns access to ack delay when high transition t cadh 4?9 ns external request delay t xad 2?? sclk
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-35 table 25-12. tft lcd controller module signal timing constants (v dd =1.8v 0.15 v, t a =0to70 c, v ext =3.3v 0.3v) parameter symbol min typ max units vertical sync pulse width tvspw vspw + 1 ? ? phclk (note1) vertical back porch delay tvbpd vbpd+1 ? ? phclk vertical front porch dealy tvfpd vfpd+1 ? ? phclk vclk pulse width tvclk 1 ? ? pvclk (note2) vclk pulse width high tvclkh 0.5 ? ? pvclk vclk pulse width low tvclkl 0.5 ? ? pvclk hsync setup to vclk falling edge tl2csetup 0.5 ? ? pvclk vden set up to vclk falling edge tde2csetup 0.5 ? ? pvclk vden hold from vclk falling edge tde2chold 0.5 ? ? pvclk vd setup to vclk falling edge tvd2csetup 0.5 ? ? pvclk vd hold from vclk falling edge tvd2chold 0.5 ? ? pvclk vsync setup to hsync falling edge tf2hsetup hspw + 1 ? ? pvclk vsync hold from hsync falling edge tf2hhold hbpd + hfpd + hozval + 3 ? ? pvclk notes: 1. hsync period 2. vclk period table 25-13. iis controller module signal timing constants (v dd = 1.2 v 0.1 v ,t a =0to70 c, v ext =3.3v 0.3v) parameter symbol min typ. max unit iislrck delay time t lrck 0?3 ns iisdo delay time t sdo 0?2 ns iisdi input setup time t sdis 5?10 ns iisdi input hold time t sdih 0?1 ns codec clock frequency f codec 1/16 ? 1 f iis_block
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-36 table 25-14. iic bus controller module signal timing (v dd =1.8v 0.15 v, t a =0to70 c, v ext =3.3v 0.3v) parameter symbol min typ. max unit scl clock frequency f scl ? ? std. 100 fast 400 khz scl high level pulse width t sclhigh std. 4.0 fast 0.6 ?? s scl low level pulse width t scllow std. 4.7 fast 1.3 ?? s bus free time between stop and start t buf std. 4.7 fast 1.3 ?? s start hold time t starts std. 4.0 fast 0.6 ?? s sda hold time t sdah std. 0 fast 0 ?std.-fast 0.9 s sda setup time t sdas std. 250 fast 100 ??ns stop setup time t stoph std. 4.0 fast 0.6 ?? s notes: std. means standard mode and fast means fast mode. 1. the iic data hold time(tsdah) is minimum 0ns. (iic data hold time is minimum 0ns for standard/fast bus mode in iic specification v2.1.) please check the data hold time of your iic device if it's 0 ns or not. 2. the iic controller supports only iic bus device(standard/fast bus mode), not c bus device. table 25-15. sd/mmc interface transmit/receive timing constants (v dd = 1.2 v 0.1 v ,t a =0to70 c, v ext =3.3v 0.3v) parameter symbol min typ. max unit sd command output delay time t sdcd 0?1 ns sd command input setup time t sdcs 5?11 ns sd command input hold time t sdch 0?1 ns sd data output delay time t sddd 0?1 ns sd data input setup time t sdds 5?11 ns sd data input hold time t sddh 0?1 ns
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-37 table 25-16. spi interface transmit/receive timing constants (v dd = 1.2 v 0.1 v ,t a =0to70 c, v ext =3.3v 0.3v) parameter symbol min typ. max unit spi mosi master output delay time t spimod 0?1 ns spi mosi slave input setup time t spisis 0?1 ns spi mosi slave input hold time t spisih 0?1 ns spi miso slave output delay time t spisod 6?18 ns spi miso master input setup time t spimis 5?15 ns spi miso master input hold time t spimih 0?1 ns table 25-17. usb electrical specifications (v dd =1.8v 0.15 v, t a =0to70 c, v ext =3.3v 0.3v) parameter symbol condition min max unit supply current suspend device iccs 10 a leakage current hi-z state input leakage ilo 0v < vin < 3.3v -10 10 a input levels differential input sensitivity vdi | (d+) ? (d-) | 0.2 v differential common mode range vcm includes vdi range 0.8 2.5 single ended receiver threshold vse 0.8 2.0 output levels static output low vol rl of 1.5kohm to 3.6v 0.2 v static output high voh rl of 15kohm to gnd 2.8 3.6 capacitance transceiver capacitance cin pin to gnd 20 pf
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-38 table 25-18. usb full speed output buffer electrical characteristics (v dd =1.8v 0.15 v, t a =0to70 c, v ext =3.3v 0.3v) parameter symbol condition min max unit driver characteristics transition time rise time fall time tr tf cl = 50pf cl = 50pf 4.0 4.0 20 20 ns rise/fall time matching trfm (tr / tf ) 90 111.1 % output signal crossover voltage vcrs 1.3 2.0 v drive output resistance zdrv steady state drive 28 44 ohm table 25-19. usb low speed output buffer electrical characteristics (v dd =1.8v 0.15 v, t a =0to70 c, v ext =3.3v 0.3v) parameter symbol condition min max unit driver characteristics 75 ns rising time tr cl = 50pf cl = 350pf 300 75 falling time tf cl = 50pf cl = 350pf 300 rise/fall time matching trfm (tr / tf ) 80 125 % output signal crossover voltage vcrs 1.3 2.0 v note: all measurement conditions are in accordance with the universal serial bus specification 1.1 final draft revision.
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. S3C2440X risc microprocessor electrical data 25-39 table 25-20. nand flash interface timing constants (v ddi, v ddalive, v ddiarm =1.8v 0.15 v, t a =0to70 c, v ddio =3.3v 0.3v) parameter symbol min max unit nfcon chip enable delay t ced ? 5.3 ns nfcon cle delay t cled ? 5.7 ns nfcon ale delay t aled ? 5.5 ns nfcon write enable delay t wed ? 5.6 ns nfcon read enable delay t red ? 5.9 ns nfcon write data setup time t wds ? 5.4 ns nfcon write data hold time t wdh 3.7 5.5 ns nfcon read data setup requirement time t rds 3 ?ns nfcon read data hold requirement time t rdh 0.3 ? ns
2003.10.15 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. electrical data S3C2440X risc microprocessor 25-40 notes
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. s3c2440 x risc microprocessor mech a nic a ld a t a 26-1 mechanical data package dimensions 14.00 14.00 0.35 ?0.05 1.22 289-fbga-1414 0.45 ?0.05 c 0.12 max 0.10 c a b 0.15 tolerance ?0.10 x2 0.15 x2 c c samsung figure 26-1. 289-fbga-1414 package dimension 1 (top view)
2003.09.25 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available specifications and information herein are subject to change without notice. mech a nic a ld a t a s3c2440 x risc microprocessor 26-2 a1 index mark 0.80 x 16 = 12.80 0.05 14.00 0.80 0.80 a b c d e f g h j k l m n p r t u 8 9 10 11 12 13 14 15 16 17 5 6 71 2 3 4 14.00 0.15 0.08 m m c c a b 289 - 0.45 0.05 tolerance 0.10 figure 26-2. 289-fbga-1414 package dimension 2 (bottom view) the recommended land open size is 0.39 ? 0.41mm diameter.

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